Streaming engine with early exit from loop levels supporting early exit loops and irregular loops

ABSTRACT

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. Upon a stream break instruction specifying one of the nested loops, the stream engine ends a current iteration of the loop. If the specified loop was not the outermost loop, the streaming engine begins an iteration of a next outer loop. If the specified loop was the outermost nested loop, the streaming engine ends the stream. The streaming engine places a vector of data elements in order in lanes within a stream head register. A stream break instruction is operable upon a vector break.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.17/163,639, filed Feb. 1, 2021, which is a continuation of U.S. patentapplication Ser. No. 15/636,669, filed Jun. 29, 2017, now U.S. Pat. No.10,908,901, each of which is incorporated by reference herein in itsentirety.

U.S. patent application No. 15/636,669 is an improvement over U.S.patent application Ser. No. 14/331,986, filed Jul. 15, 2014, now U.S.Pat. No. 9,606,803, entitled HIGHLY INTEGRATED SCALABLE, FLEXIBLE DSPMEGAMODULE ARCHITECTURE, which claims priority from U.S. ProvisionalPatent Application Ser. No. 61/846,148 filed Jul. 15, 2013.

TECHNICAL FIELD OF THE INVENTION

The technical field of this invention is digital data processing andmore specifically control of streaming engine used for operand fetching.

BACKGROUND OF THE INVENTION

Modern digital signal processors (DSP) faces multiple challenges.Workloads continue to increase, requiring increasing bandwidth. Systemson a chip (SOC) continue to grow in size and complexity. Memory systemlatency severely impacts certain classes of algorithms. As transistorsget smaller, memories and registers become less reliable. As softwarestacks get larger, the number of potential interactions and errorsbecomes larger.

Memory bandwidth and scheduling are a problem for digital signalprocessors operating on real-time data. Digital signal processorsoperating on real-time data typically receive an input data stream,perform a filter function on the data stream (such as encoding ordecoding) and output a transformed data stream. The system is calledreal-time because the application fails if the transformed data streamis not available for output when scheduled. Typical video encodingrequires a predictable but non-sequential input data pattern. Often thecorresponding memory accesses are difficult to achieve within availableaddress generation and memory access resources. A typical applicationrequires memory access to load data registers in a data register fileand then supply to functional units which perform the data processing.

SUMMARY OF THE INVENTION

This invention is a digital data processor having a streaming enginewhich recalls from memory a stream of an instruction specified sequenceof a predetermined number of data elements in plural nested loops foruse in order by data processing functional units. A predetermined codingin an operand field of an instruction specifies stream data as anoperand for that instruction. Each data element has a predetermined sizeand data type. Data elements are packed in lanes of the defined datawidth in a vector stream head register. The streaming engine ends datarecall upon a stream end instruction or recall of all data elements inthe stream.

A stream start instruction begins stream recall and specifies theparameters of the data stream. Each stream start instruction preferablyspecifies a number of enabled nested loops within a predeterminedmaximum. If a stream break instruction specifies a loop that is greaterthan the number of enabled loops, the streaming engine ends the stream.

Preferably the stream break instruction is effective upon a next vectorboundary when the stream head register lanes are filled. A vector lengthunit may limit lane use to less than the full data width of the streamhead register. In that event, filling all the lanes of the stream headregister occurs when all lanes within the vector length are filled.

Each stream start instruction preferably may specify a transposedisabled mode or a transpose enabled mode. An address generator swapsthe parameters for the inner most loop and the next inner most loop whentranspose is enabled. In the same manner, the streaming engine swaps theparameters for the inner most loop and the next inner most loop whentranspose is enabled. Thus when transpose is enabled a stream breakinstruction specifying the inner most loop ends a current iteration ofthe next inner most nested loop. Also when transpose is enabled a streambreak instruction specifying the next inner most loop ends the currentiteration of the inner most loop.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects of this invention are illustrated in thedrawings, in which:

FIG. 1 illustrates a dual scalar/vector datapath processor according toone embodiment of this invention;

FIG. 2 illustrates the registers and functional units in the dualscalar/vector datapath processor illustrated in FIG. 1 ;

FIG. 3 illustrates a global scalar register file; FIG. 4 illustrates alocal scalar register file shared by arithmetic functional units;

FIG. 5 illustrates a local scalar register file shared by multiplyfunctional units;

FIG. 6 illustrates a local scalar register file shared by load/storeunits;

FIG. 7 illustrates a global vector register file;

FIG. 8 illustrates a predicate register file;

FIG. 9 illustrates a local vector register file shared by arithmeticfunctional units;

FIG. 10 illustrates a local vector register file shared by multiply andcorrelation functional units;

FIG. 11 illustrates pipeline phases of a central processing unitaccording to a preferred embodiment of this invention;

FIG. 12 illustrates sixteen instructions of a single fetch packet;

FIG. 13 illustrates an example of instruction coding of instructionsused by this invention;

FIG. 14 illustrates a bit coding of a condition code extension slot 0;

FIG. 15 illustrates a bit coding of a condition code extension slot 1;

FIG. 16 illustrates a bit coding of a constant extension slot 0;

FIG. 17 is a partial block diagram illustrating constant extension;

FIG. 18 illustrates a carry control for SIMD operations according tothis invention;

FIG. 19 illustrates a conceptual view of streaming engines of thisinvention;

FIG. 20 illustrates a sequence of formatting operations of thisinvention;

FIG. 21 illustrates a first example of lane allocation in a vector;

FIG. 22 illustrates a second example of lane allocation in a vector;

FIG. 23 illustrates a basic two dimensional stream;

FIG. 24 illustrates an order of elements within the example stream ofFIG. 23 ;

FIG. 25 illustrates extracting a smaller rectangle from a largerrectangle;

FIG. 26 illustrates how a streaming engine would fetch a stream of thisexample with a transposition granularity of 4 bytes;

FIG. 27 illustrates how a streaming engine would fetch a stream of thisexample with a transposition granularity of 8 bytes;

FIG. 28 illustrates details of a streaming engine of this invention;

FIG. 29 illustrates a stream template register of this invention;

FIG. 30 illustrates sub-field definitions of a flags field of a streamtemplate register of this invention;

FIG. 31 is a partial schematic diagram of a streaming engine addressgenerator illustrating generation of the loop address and loop count;and

FIG. 32 illustrates a partial schematic diagram showing a streamingengine supply of data of this invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1 illustrates a dual scalar/vector datapath processor according toa preferred embodiment of this invention. Processor 100 includesseparate level one instruction cache (L1I) 121 and level one data cache(L1D) 123. Processor 100 includes a level two combined instruction/datacache (L2) 130 that holds both instructions and data. FIG. 1 illustratesconnection between level one instruction cache 121 and level twocombined instruction/data cache 130 (bus 142). FIG. 1 illustratesconnection between level one data cache 123 and level two combinedinstruction/data cache 130 (bus 145). In the preferred embodiment ofprocessor 100 level two combined instruction/data cache 130 stores bothinstructions to back up level one instruction cache 121 and data to backup level one data cache 123. In the preferred embodiment level twocombined instruction/data cache 130 is further connected to higher levelcache and/or main memory in a manner known in the art and notillustrated in FIG. 1 . In the preferred embodiment central processingunit core 110, level one instruction cache 121, level one data cache 123and level two combined instruction/data cache 130 are formed on a singleintegrated circuit. This signal integrated circuit optionally includesother circuits.

Central processing unit core 110 fetches instructions from level oneinstruction cache 121 as controlled by instruction fetch unit 111.Instruction fetch unit 111 determines the next instructions to beexecuted and recalls a fetch packet sized set of such instructions. Thenature and size of fetch packets are further detailed below. As known inthe art, instructions are directly fetched from level one instructioncache 121 upon a cache hit (if these instructions are stored in levelone instruction cache 121). Upon a cache miss (the specified instructionfetch packet is not stored in level one instruction cache 121), theseinstructions are sought in level two combined cache 130. In thepreferred embodiment the size of a cache line in level one instructioncache 121 equals the size of a fetch packet. The memory locations ofthese instructions are either a hit in level two combined cache 130 or amiss. A hit is serviced from level two combined cache 130. A miss isserviced from a higher level of cache (not illustrated) or from mainmemory (not illustrated). As is known in the art, the requestedinstruction may be simultaneously supplied to both level one instructioncache 121 and central processing unit core 110 to speed use.

In the preferred embodiment of this invention, central processing unitcore 110 includes plural functional units to perform instructionspecified data processing tasks. Instruction dispatch unit 112determines the target functional unit of each fetched instruction. Inthe preferred embodiment central processing unit 110 operates as a verylong instruction word (VLIW) processor capable of operating on pluralinstructions in corresponding functional units simultaneously.Preferably a complier organizes instructions in execute packets that areexecuted together. Instruction dispatch unit 112 directs eachinstruction to its target functional unit. The functional unit assignedto an instruction is completely specified by the instruction produced bya compiler. The hardware of central processing unit core 110 has no partin this functional unit assignment. In the preferred embodimentinstruction dispatch unit 112 may operate on plural instructions inparallel. The number of such parallel instructions is set by the size ofthe execute packet. This will be further detailed below.

One part of the dispatch task of instruction dispatch unit 112 isdetermining whether the instruction is to execute on a functional unitin scalar datapath side A 115 or vector datapath side B 116. Aninstruction bit within each instruction called the s bit determineswhich datapath the instruction controls. This will be further detailedbelow.

Instruction decode unit 113 decodes each instruction in a currentexecute packet. Decoding includes identification of the functional unitperforming the instruction, identification of registers used to supplydata for the corresponding data processing operation from among possibleregister files and identification of the register destination of theresults of the corresponding data processing operation. As furtherexplained below, instructions may include a constant field in place ofone register number operand field. The result of this decoding issignals for control of the target functional unit to perform the dataprocessing operation specified by the corresponding instruction on thespecified data.

Central processing unit core 110 includes control registers 114. Controlregisters 114 store information for control of the functional units inscalar datapath side A 115 and vector datapath side B 116 in a mannernot relevant to this invention. This information could be modeinformation or the like.

The decoded instructions from instruction decode 113 and informationstored in control registers 114 are supplied to scalar datapath side A115 and vector datapath side B 116. As a result functional units withinscalar datapath side A 115 and vector datapath side B 116 performinstruction specified data processing operations upon instructionspecified data and store the results in an instruction specified dataregister or registers. Each of scalar datapath side A 115 and vectordatapath side B 116 include plural functional units that preferablyoperate in parallel. These will be further detailed below in conjunctionwith FIG. 2 . There is a datapath 117 between scalar datapath side A 115and vector datapath side B 116 permitting data exchange.

Central processing unit core 110 includes further non-instruction basedmodules. Emulation unit 118 permits determination of the machine stateof central processing unit core 110 in response to instructions. Thiscapability will typically be employed for algorithmic development.Interrupts/exceptions unit 119 enable central processing unit core 110to be responsive to external, asynchronous events (interrupts) and torespond to attempts to perform improper operations (exceptions).

Central processing unit core 110 includes streaming engine 125.Streaming engine 125 supplies two data streams from predeterminedaddresses typically cached in level two combined cache 130 to registerfiles of vector datapath side B. This provides controlled data movementfrom memory (as cached in level two combined cache 130) directly tofunctional unit operand inputs. This is further detailed below.

FIG. 1 illustrates exemplary data widths of busses between variousparts. Level one instruction cache 121 supplies instructions toinstruction fetch unit 111 via bus 141. Bus 141 is preferably a 512-bitbus. Bus 141 is unidirectional from level one instruction cache 121 tocentral processing unit 110. Level two combined cache 130 suppliesinstructions to level one instruction cache 121 via bus 142. Bus 142 ispreferably a 512-bit bus. Bus 142 is unidirectional from level twocombined cache 130 to level one instruction cache 121.

Level one data cache 123 exchanges data with register files in scalardatapath side A 115 via bus 143. Bus 143 is preferably a 64-bit bus.Level one data cache 123 exchanges data with register files in vectordatapath side B 116 via bus 144. Bus 144 is preferably a 512-bit bus.Busses 143 and 144 are illustrated as bidirectional supporting bothcentral processing unit 110 data reads and data writes. Level one datacache 123 exchanges data with level two combined cache 130 via bus 145.Bus 145 is preferably a 512-bit bus. Bus 145 is illustrated asbidirectional supporting cache service for both central processing unit110 data reads and data writes.

As known in the art, CPU data requests are directly fetched from levelone data cache 123 upon a cache hit (if the requested data is stored inlevel one data cache 123). Upon a cache miss (the specified data is notstored in level one data cache 123), this data is sought in level twocombined cache 130. The memory locations of this requested data iseither a hit in level two combined cache 130 or a miss. A hit isserviced from level two combined cache 130. A miss is serviced fromanother level of cache (not illustrated) or from main memory (notillustrated). As is known in the art, the requested instruction may besimultaneously supplied to both level one data cache 123 and centralprocessing unit core 110 to speed use.

Level two combined cache 130 supplies data of a first data stream tostreaming engine 125 via bus 146. Bus 146 is preferably a 512-bit bus.Streaming engine 125 supplies data of this first data stream tofunctional units of vector datapath side B 116 via bus 147. Bus 147 ispreferably a 512-bit bus. Level two combined cache 130 supplies data ofa second data stream to streaming engine 125 via bus 148. Bus 148 ispreferably a 512-bit bus. Streaming engine 125 supplies data of thissecond data stream to functional units of vector datapath side B 116 viabus 149. Bus 149 is preferably a 512-bit bus. Busses 146, 147, 148 and149 are illustrated as unidirectional from level two combined cache 130to streaming engine 125 and to vector datapath side B 116 in accordancewith the preferred embodiment of this invention.

Steaming engine data requests are directly fetched from level twocombined cache 130 upon a cache hit (if the requested data is stored inlevel two combined cache 130). Upon a cache miss (the specified data isnot stored in level two combined cache 130), this data is sought fromanother level of cache (not illustrated) or from main memory (notillustrated). It is technically feasible in some embodiments for levelone data cache 123 to cache data not stored in level two combined cache130. If such operation is supported, then upon a streaming engine datarequest that is a miss in level two combined cache 130, level twocombined cache 130 should snoop level one data cache 1233 for the streamengine requested data. If level one data cache 123 stores this data itssnoop response would include the data, which is then supplied to servicethe streaming engine request. If level one data cache 123 does not storethis data its snoop response would indicate this and level two combinedcache 130 must service this streaming engine request from another levelof cache (not illustrated) or from main memory (not illustrated).

In the preferred embodiment of this invention, both level one data cache123 and level two combined cache 130 may be configured as selectedamounts of cache or directly addressable memory in accordance with U.S.Pat. No. 6,606,686 entitled UNIFIED MEMORY SYSTEM ARCHITECTURE INCLUDINGCACHE AND DIRECTLY ADDRESSABLE STATIC RANDOM ACCESS MEMORY.

FIG. 2 illustrates further details of functional units and registerfiles within scalar datapath side A 115 and vector datapath side B 116.Scalar datapath side A 115 includes global scalar register file 211,L1/S1 local register file 212, M1/N1 local register file 213 and D1/D2local register file 214. Scalar datapath side A 115 includes L1 unit221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225 and D2 unit 226.Vector datapath side B 116 includes global vector register file 231,L2/S2 local register file 232, M2/N2/C local register file 233 andpredicate register file 234. Vector datapath side B 116 includes L2 unit241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245 and P unit 246.There are limitations upon which functional units may read from or writeto which register files. These will be detailed below.

Scalar datapath side A 115 includes L1 unit 221. L1 unit 221 generallyaccepts two 64-bit operands and produces one 64-bit result. The twooperands are each recalled from an instruction specified register ineither global scalar register file 211 or L1/S1 local register file 212.L1 unit 221 preferably performs the following instruction selectedoperations: 64-bit add/subtract operations; 32-bit min/max operations;8-bit Single Instruction Multiple Data (SIMD) instructions such as sumof absolute value, minimum and maximum determinations; circular min/maxoperations; and various move operations between register files. Theresult may be written into an instruction specified register of globalscalar register file 211, L1/S1 local register file 212, M1/N1 localregister file 213 or D1/D2 local register file 214.

Scalar datapath side A 115 includes S1 unit 222. S1 unit 222 generallyaccepts two 64-bit operands and produces one 64-bit result. The twooperands are each recalled from an instruction specified register ineither global scalar register file 211 or L1/S1 local register file 212.S1 unit 222 preferably performs the same type operations as L1 unit 221.There optionally may be slight variations between the data processingoperations supported by L1 unit 221 and S1 unit 222. The result may bewritten into an instruction specified register of global scalar registerfile 211, L1/S1 local register file 212, M1/N1 local register file 213or D1/D2 local register file 214.

Scalar datapath side A 115 includes M1 unit 223. M1 unit 223 generallyaccepts two 64-bit operands and produces one 64-bit result. The twooperands are each recalled from an instruction specified register ineither global scalar register file 211 or M1/N1 local register file 213.M1 unit 223 preferably performs the following instruction selectedoperations: 8-bit multiply operations; complex dot product operations;32-bit bit count operations; complex conjugate multiply operations; andbit-wise Logical Operations, moves, adds and subtracts. The result maybe written into an instruction specified register of global scalarregister file 211, L1/S1 local register file 212, M1/N1 local registerfile 213 or D1/D2 local register file 214.

Scalar datapath side A 115 includes N1 unit 224. N1 unit 224 generallyaccepts two 64-bit operands and produces one 64-bit result. The twooperands are each recalled from an instruction specified register ineither global scalar register file 211 or M1/N1 local register file 213.N1 unit 224 preferably performs the same type operations as M1 unit 223.There may be certain double operations (called dual issued instructions)that employ both the M1 unit 223 and the N1 unit 224 together. Theresult may be written into an instruction specified register of globalscalar register file 211, L1/S1 local register file 212, M1/N1 localregister file 213 or D1/D2 local register file 214.

Scalar datapath side A 115 includes D1 unit 225 and D2 unit 226. D1 unit225 and D2 unit 226 generally each accept two 64-bit operands and eachproduce one 64-bit result. D1 unit 225 and D2 unit 226 generally performaddress calculations and corresponding load and store operations. D1unit 225 is used for scalar loads and stores of 64 bits. D2 unit 226 isused for vector loads and stores of 512 bits. D1 unit 225 and D2 unit226 preferably also perform: swapping, pack and unpack on the load andstore data; 64-bit SIMD arithmetic operations; and 64-bit bit-wiselogical operations. D1/D2 local register file 214 will generally storebase and offset addresses used in address calculations for thecorresponding loads and stores. The two operands are each recalled froman instruction specified register in either global scalar register file211 or D1/D2 local register file 214. The calculated result may bewritten into an instruction specified register of global scalar registerfile 211, L1/S1 local register file 212, M1/N1 local register file 213or D1/D2 local register file 214.

Vector datapath side B 116 includes L2 unit 241. L2 unit 241 generallyaccepts two 512-bit operands and produces one 512-bit result. The twooperands are each recalled from an instruction specified register ineither global vector register file 231, L2/S2 local register file 232 orpredicate register file 234. L2 unit 241 preferably performsinstructions similar to L1 unit 221 except on wider 512-bit data. Theresult may be written into an instruction specified register of globalvector register file 231, L2/S2 local register file 232, M2/N2/C localregister file 233 or predicate register file 234.

Vector datapath side B 116 includes S2 unit 242. S2 unit 242 generallyaccepts two 512-bit operands and produces one 512-bit result. The twooperands are each recalled from an instruction specified register ineither global vector register file 231, L2/S2 local register file 232 orpredicate register file 234. S2 unit 242 preferably performsinstructions similar to S1 unit 222. The result may be written into aninstruction specified register of global vector register file 231, L2/S2local register file 232, M2/N2/C local register file 233 or predicateregister file 234.

Vector datapath side B 116 includes M2 unit 243. M2 unit 243 generallyaccepts two 512-bit operands and produces one 512-bit result. The twooperands are each recalled from an instruction specified register ineither global vector register file 231 or M2/N2/C local register file233. M2 unit 243 preferably performs instructions similar to M1 unit 223except on wider 512-bit data. The result may be written into aninstruction specified register of global vector register file 231, L2/S2local register file 232 or M2/N2/C local register file 233.

Vector datapath side B 116 includes N2 unit 244. N2 unit 244 generallyaccepts two 512-bit operands and produces one 512-bit result. The twooperands are each recalled from an instruction specified register ineither global vector register file 231 or M2/N2/C local register file233. N2 unit 244 preferably performs the same type operations as M2 unit243. There may be certain double operations (called dual issuedinstructions) that employ both M2 unit 243 and the N2 unit 244 together.The result may be written into an instruction specified register ofglobal vector register file 231, L2/S2 local register file 232 orM2/N2/C local register file 233.

Vector datapath side B 116 includes C unit 245. C unit 245 generallyaccepts two 512-bit operands and produces one 512-bit result. The twooperands are each recalled from an instruction specified register ineither global vector register file 231 or M2/N2/C local register file233. C unit 245 preferably performs: “Rake” and “Search” instructions;up to 512 2-bit PN*8-bit multiplies I/O complex multiplies per clockcycle; 8-bit and 16-bit Sum-of-Absolute-Difference (SAD) calculations,up to 512 SADs per clock cycle; horizontal add and horizontal min/maxinstructions; and vector permutes instructions. C unit 245 also contains4 vector control registers (CUCR0 to CUCR3) used to control certainoperations of C unit 245 instructions. Control registers CUCR0 to CUCR3are used as operands in certain C unit 245 operations. Control registersCUCR0 to CUCR3 are preferably used: in control of a general permutationinstruction (VPERM); and as masks for SIMD multiple DOT productoperations (DOTPM) and SIMD multiple Sum-of-Absolute-Difference (SAD)operations. Control register CUCR0 is preferably used to store thepolynomials for Galios Field Multiply operations (GFMPY). Controlregister CUCR1 is preferably used to store the Galois field polynomialgenerator function.

Vector datapath side B 116 includes P unit 246. P unit 246 performsbasic logic operations on registers of local predicate register file234. P unit 246 has direct access to read from and write to predicationregister file 234. These operations include single register unaryoperations such as: NEG (negate) which inverts each bit of the singleregister; BITCNT (bit count) which returns a count of the number of bitsin the single register having a predetermined digital state (1 or 0);RMBD (right most bit detect) which returns a number of bit positionsfrom the least significant bit position (right most) to a first bitposition having a predetermined digital state (1 or 0); DECIMATE whichselects every instruction specified Nth (1, 2, 4, etc.) bit to output;and EXPAND which replicates each bit an instruction specified N times(2, 4, etc.). These operations include two register binary operationssuch as: AND a bitwise AND of data of the two registers; NAND a bitwiseAND and negate of data of the two registers; OR a bitwise OR of data ofthe two registers; NOR a bitwise OR and negate of data of the tworegisters; and XOR exclusive OR of data of the two registers. Theseoperations include transfer of data from a predicate register ofpredicate register file 234 to another specified predicate register orto a specified data register in global vector register file 231. Acommonly expected use of P unit 246 includes manipulation of the SIMDvector comparison results for use in control of a further SIMD vectoroperation. The BITCNT instruction may be used to count the number of 1'sin a predicate register to determine the number of valid data elementsfrom a predicate register.

FIG. 3 illustrates global scalar register file 211. There are 16independent 64-bit wide scalar registers designated A0 to A15. Eachregister of global scalar register file 211 can be read from or writtento as 64-bits of scalar data. All scalar datapath side A 115 functionalunits (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225and D2 unit 226) can read or write to global scalar register file 211.Global scalar register file 211 may be read as 32-bits or as 64-bits andmay only be written to as 64-bits. The instruction executing determinesthe read data size. Vector datapath side B 116 functional units (L2 unit241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245 and P unit 246)can read from global scalar register file 211 via crosspath 117 underrestrictions that will be detailed below.

FIG. 4 illustrates D1/D2 local register file 214. There are 16independent 64-bit wide scalar registers designated D0 to D16. Eachregister of D1/D2 local register file 214 can be read from or written toas 64-bits of scalar data. All scalar datapath side A 115 functionalunits (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225and D2 unit 226) can write to global scalar register file 211. Only D1unit 225 and D2 unit 226 can read from D1/D2 local scalar register file214. It is expected that data stored in D1/D2 local scalar register file214 will include base addresses and offset addresses used in addresscalculation.

FIG. 5 illustrates L1/S1 local register file 212. The embodimentillustrated in FIG. 5 has 8 independent 64-bit wide scalar registersdesignated AL0 to AL7. The preferred instruction coding (see FIG. 13 )permits M2/N2/C local register file 233 to include up to 16 registers.The embodiment of FIG. 5 implements only 8 registers to reduce circuitsize and complexity. Each register of L1/S1 local register file 212 canbe read from or written to as 64-bits of scalar data. All scalardatapath side A 115 functional units (L1 unit 221, S1 unit 222, M1 unit223, N1 unit 224, D1 unit 225 and D2 unit 226) can write to L1/S1 localscalar register file 212. Only L1 unit 221 and S1 unit 222 can read fromL1/S1 local scalar register file 212.

FIG. 6 illustrates M1/N1 local register file 213. The embodimentillustrated in FIG. 6 has 8 independent 64-bit wide scalar registersdesignated AM0 to AM7. The preferred instruction coding (see FIG. 13 )permits M1/N1 local register file 213 to include up to 16 registers. Theembodiment of FIG. 6 implements only 8 registers to reduce circuit sizeand complexity. Each register of M1/N1 local register file 213 can beread from or written to as 64-bits of scalar data. All scalar datapathside A 115 functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1unit 224, D1 unit 225 and D2 unit 226) can write to M1/N1 local scalarregister file 213. Only M1 unit 223 and N1 unit 224 can read from M1/N1local scalar register file 213.

FIG. 7 illustrates global vector register file 231. There are 16independent 512-bit wide vector registers. Each register of globalvector register file 231 can be read from or written to as 64-bits ofscalar data designated B0 to B15. Each register of global vectorregister file 231 can be read from or written to as 512-bits of vectordata designated VB0 to VB15. The instruction type determines the datasize. All vector datapath side B 116 functional units (L2 unit 241, S2unit 242, M2 unit 243, N2 unit 244, C unit 245 and P unit 246) can reador write to global vector register file 231. Scalar datapath side A 115functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1unit 225 and D2 unit 226) can read from global vector register file 231via crosspath 117 under restrictions that will be detailed below.

FIG. 8 illustrates P local register file 234. There are 8 independent64-bit wide registers designated P0 to P15. Each register of P localregister file 234 can be read from or written to as 64-bits of scalardata. Vector datapath side B 116 functional units L2 unit 241, S2 unit242, C unit 244 and P unit 246 can write to P local register file 234.Only L2 unit 241, S2 unit 242 and P unit 246 can read from P localscalar register file 234. A commonly expected use of P local registerfile 234 includes: writing one bit SIMD vector comparison results fromL2 unit 241, S2 unit 242 or C unit 244; manipulation of the SIMD vectorcomparison results by P unit 246; and use of the manipulated results incontrol of a further SIMD vector operation.

FIG. 9 illustrates L2/S2 local register file 232. The embodimentillustrated in FIG. 9 has 8 independent 512-bit wide vector registers.The preferred instruction coding (see FIG. 13 ) permits L2/S2 localregister file 232 to include up to 16 registers. The embodiment of FIG.9 implements only 8 registers to reduce circuit size and complexity.Each register of L2/S2 local vector register file 232 can be read fromor written to as 64-bits of scalar data designated BL0 to BL7. Eachregister of L2/S2 local vector register file 232 can be read from orwritten to as 512-bits of vector data designated VBL0 to VBL7. Theinstruction type determines the data size. All vector datapath side B116 functional units (L2 unit 241, S2 unit 242, M2 unit 243, N2 unit244, C unit 245 and P unit 246) can write to L2/ S2 local vectorregister file 232. Only L2 unit 241 and S2 unit 242 can read from L2/ S2local vector register file 232.

FIG. 10 illustrates M2/N2/C local register file 233. The embodimentillustrated in FIG. 10 has 8 independent 512-bit wide vector registers.The preferred instruction coding (see FIG. 13 ) permits L1/S1 localregister file 212 to include up to 16 registers. The embodiment of FIG.10 implements only 8 registers to reduce circuit size and complexity.Each register of M2/N2/C local vector register file 233 can be read fromor written to as 64-bits of scalar data designated BM0 to BM7. Eachregister of M2/N2/C local vector register file 233 can be read from orwritten to as 512-bits of vector data designated VBM0 to VBM7. Allvector datapath side B 116 functional units (L2 unit 241, S2 unit 242,M2 unit 243, N2 unit 244, C unit 245 and P unit 246) can write toM2/N2/C local vector register file 233. Only M2 unit 243, N2 unit 244and C unit 245 can read from M2/N2/C local vector register file 233.

The provision of global register files accessible by all functionalunits of a side and local register files accessible by only some of thefunctional units of a side is a design choice. This invention could bepracticed employing only one type of register file corresponding to thedisclosed global register files.

Crosspath 117 permits limited exchange of data between scalar datapathside A 115 and vector datapath side B 116. During each operational cycleone 64-bit data word can be recalled from global scalar register file A211 for use as an operand by one or more functional units of vectordatapath side B 116 and one 64-bit data word can be recalled from globalvector register file 231 for use as an operand by one or more functionalunits of scalar datapath side A 115. Any scalar datapath side A 115functional unit (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1unit 225 and D2 unit 226) may read a 64-bit operand from global vectorregister file 231. This 64-bit operand is the least significant bits ofthe 512-bit data in the accessed register of global vector register file231. Plural scalar datapath side A 115 functional units may employ thesame 64-bit crosspath data as an operand during the same operationalcycle. However, only one 64-bit operand is transferred from vectordatapath side B 116 to scalar datapath side A 115 in any singleoperational cycle. Any vector datapath side B 116 functional unit (L2unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245 and P unit246) may read a 64-bit operand from global scalar register file 211. Ifthe corresponding instruction is a scalar instruction, the crosspathoperand data is treated as any other 64-bit operand. If thecorresponding instruction is a vector instruction, the upper 448 bits ofthe operand are zero filled. Plural vector datapath side B 116functional units may employ the same 64-bit crosspath data as an operandduring the same operational cycle. Only one 64-bit operand istransferred from scalar datapath side A 115 to vector datapath side B116 in any single operational cycle.

Streaming engine 125 transfers data in certain restricted circumstances.Streaming engine 125 controls two data streams. A stream consists of asequence of elements of a particular type. Programs that operate onstreams read the data sequentially, operating on each element in turn.Every stream has the following basic properties. The stream data have awell-defined beginning and ending in time. The stream data have fixedelement size and type throughout the stream. The stream data have fixedsequence of elements. Thus programs cannot seek randomly within thestream. The stream data is read-only while active. Programs cannot writeto a stream while simultaneously reading from it. Once a stream isopened streaming engine 125: calculates the address; fetches the defineddata type from level two unified cache (which may require cache servicefrom a higher level memory); performs data type manipulation such aszero extension, sign extension, data element sorting/swapping such asmatrix transposition; and delivers the data directly to the programmeddata register file within CPU 110. Streaming engine 125 is thus usefulfor real-time digital filtering operations on well-behaved data.Streaming engine 125 frees these memory fetch tasks from thecorresponding CPU enabling other processing functions.

Streaming engine 125 provides the following benefits. Streaming engine125 permits multi-dimensional memory accesses. Streaming engine 125increases the available bandwidth to the functional units. Streamingengine 125 minimizes the number of cache miss stalls since the streambuffer bypasses level one data cache 123. Streaming engine 125 reducesthe number of scalar operations required to maintain a loop. Streamingengine 125 manages address pointers. Streaming engine 125 handlesaddress generation automatically freeing up the address generationinstruction slots and D1 unit 225 and D2 unit 226 for othercomputations.

CPU 110 operates on an instruction pipeline. Instructions are fetched ininstruction packets of fixed length further described below. Allinstructions require the same number of pipeline phases for fetch anddecode, but require a varying number of execute phases.

FIG. 11 illustrates the following pipeline phases: program fetch phase1110, dispatch and decode phases 1120 and execution phases 1130. Programfetch phase 1110 includes three stages for all instructions. Dispatchand decode phases 1120 include three stages for all instructions.Execution phase 1130 includes one to four stages dependent on theinstruction.

Fetch phase 1110 includes program address generation stage 1111 (PG),program access stage 1112 (PA) and program receive stage 1113 (PR).During program address generation stage 1111 (PG), the program addressis generated in the CPU and the read request is sent to the memorycontroller for the level one instruction cache L1I. During the programaccess stage 1112 (PA) the level one instruction cache L1I processes therequest, accesses the data in its memory and sends a fetch packet to theCPU boundary. During the program receive stage 1113 (PR) the CPUregisters the fetch packet.

Instructions are always fetched sixteen 32-bit wide slots, constitutinga fetch packet, at a time. FIG. 12 illustrates 16 instructions 1201 to1216 of a single fetch packet. Fetch packets are aligned on 512-bit(16-word) boundaries. The preferred embodiment employs a fixed 32-bitinstruction length. Fixed length instructions are advantageous forseveral reasons. Fixed length instructions enable easy decoderalignment. A properly aligned instruction fetch can load pluralinstructions into parallel instruction decoders. Such a properly alignedinstruction fetch can be achieved by predetermined instruction alignmentwhen stored in memory (fetch packets aligned on 512-bit boundaries)coupled with a fixed instruction packet fetch. An aligned instructionfetch permits operation of parallel decoders on instruction-sizedfetched bits. Variable length instructions require an initial step oflocating each instruction boundary before they can be decoded. A fixedlength instruction set generally permits more regular layout ofinstruction fields. This simplifies the construction of each decoderwhich is an advantage for a wide issue VLIW central processor.

The execution of the individual instructions is partially controlled bya p bit in each instruction. This p bit is preferably bit 0 of the32-bit wide slot. The p bit determines whether an instruction executesin parallel with a next instruction. Instructions are scanned from lowerto higher address. If the p bit of an instruction is 1, then the nextfollowing instruction (higher memory address) is executed in parallelwith (in the same cycle as) that instruction. If the p bit of aninstruction is then the next following instruction is executed in thecycle after the instruction.

CPU 110 and level one instruction cache L1I 121 pipelines are de-coupledfrom each other. Fetch packet returns from level one instruction cacheL1I can take different number of clock cycles, depending on externalcircumstances such as whether there is a hit in level one instructioncache 121 or a hit in level two combined cache 130. Therefore programaccess stage 1112 (PA) can take several clock cycles instead of 1 clockcycle as in the other stages.

The instructions executing in parallel constitute an execute packet. Inthe preferred embodiment an execute packet can contain up to sixteeninstructions. No two instructions in an execute packet may use the samefunctional unit. A slot is one of five types: 1) a self-containedinstruction executed on one of the functional units of CPU 110 (L1 unit221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, D2 unit 226, L2unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245 and P unit246); 2) a unitless instruction such as a NOP (no operation) instructionor multiple NOP instruction; 3) a branch instruction; 4) a constantfield extension; and a conditional code extension. Some of these slottypes will be further explained below.

Dispatch and decode phases 1110 include instruction dispatch toappropriate execution unit stage 1121 (DS), instruction pre-decode stage1122 (DC1); and instruction decode, operand reads stage 1222 (DC2).During instruction dispatch to appropriate execution unit stage 1121(DS), the fetch packets are split into execute packets and assigned tothe appropriate functional units. During the instruction pre-decodestage 1122 (DC1) the source registers, destination registers andassociated paths are decoded for the execution of the instructions inthe functional units. During the instruction decode, operand reads stage1123 (DC2) more detailed unit decodes are done, as well as readingoperands from the register files.

Execution phases 1130 includes execution stages 1131 to 1135 (E1 to E5).Different types of instructions require different numbers of thesestages to complete their execution. These stages of the pipeline play animportant role in understanding the device state at CPU cycleboundaries.

During execute 1 stage 1131 (E1) the conditions for the instructions areevaluated and operands are operated on. As illustrated in FIG. 11 ,execute 1 stage 1131 may receive operands from a stream buffer 1141 andone of the register files shown schematically as 1142. For load andstore instructions, address generation is performed and addressmodifications are written to a register file. For branch instructions,branch fetch packet in PG phase 1111 is affected. As illustrated in FIG.11 , load and store instructions access memory here shown schematicallyas memory 1151. For single-cycle instructions, results are written to adestination register file. This assumes that any conditions for theinstructions are evaluated as true. If a condition is evaluated asfalse, the instruction does not write any results or have any pipelineoperation after execute 1 stage 1131.

During execute 2 stage 1132 (E2) load instructions send the address tomemory. Store instructions send the address and data to memory.Single-cycle instructions that saturate results set the SAT bit in thecontrol status register (CSR) if saturation occurs. For 2-cycleinstructions, results are written to a destination register file.

During execute 3 stage 1133 (E3) data memory accesses are performed. Anymultiply instructions that saturate results set the SAT bit in thecontrol status register (CSR) if saturation occurs. For 3-cycleinstructions, results are written to a destination register file.

During execute 4 stage 1134 (E4) load instructions bring data to the CPUboundary. For 4-cycle instructions, results are written to a destinationregister file.

During execute 5 stage 1135 (E5) load instructions write data into aregister. This is illustrated schematically in FIG. 11 with input frommemory 1151 to execute 5 stage 1135.

FIG. 13 illustrates an example of the instruction coding 1300 offunctional unit instructions used by this invention. Those skilled inthe art would realize that other instruction codings are feasible andwithin the scope of this invention. Each instruction consists of 32 bitsand controls the operation of one of the individually controllablefunctional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1unit 225, D2 unit 226, L2 unit 241, S2 unit 242, M2 unit 243, N2 unit244, C unit 245 and P unit 246). The bit fields are defined as follows.

The creg field 1301 (bits 29 to 31) and the z bit 1302 (bit 28) areoptional fields used in conditional instructions. These bits are usedfor conditional instructions to identify the predicate register and thecondition. The z bit 1302 (bit 28) indicates whether the predication isbased upon zero or not zero in the predicate register. If z=1, the testis for equality with zero. If z=0, the test is for nonzero. The case ofcreg=0 and z=0 is treated as always true to allow unconditionalinstruction execution. The creg field 1301 and the z field 1302 areencoded in the instruction as shown in Table 1.

TABLE 1 Conditional creg z Register 31 30 29 28 Unconditional 0 0 0 0Reserved 0 0 0 1 A0 0 0 1 z A1 0 1 0 z A2 0 1 1 z A3 1 0 0 z A4 1 0 1 zA5 1 1 0 z Reserved 1 1 x x

Execution of a conditional instruction is conditional upon the valuestored in the specified data register. This data register is in theglobal scalar register file 211 for all functional units. Note that “z”in the z bit column refers to the zero/not zero comparison selectionnoted above and “x” is a don't care state. This coding can only specifya subset of the 16 global registers as predicate registers. Thisselection was made to preserve bits in the instruction coding. Note thatunconditional instructions do not have these optional bits. Forunconditional instructions these bits in fields 1301 and 1302 (28 to 31)are preferably used as additional opcode bits.

The dst field 1303 (bits 23 to 27) specifies a register in acorresponding register file as the destination of the instructionresults.

The src2/cst field 1304 (bits 18 to 22) has several meanings dependingon the instruction opcode field (bits 3 to 12 for all instructions andadditionally bits 28 to 31 for unconditional instructions). The firstmeaning specifies a register of a corresponding register file as thesecond operand. The second meaning is an immediate constant. Dependingon the instruction type, this is treated as an unsigned integer and zeroextended to a specified data length or is treated as a signed integerand sign extended to the specified data length.

The src1 field 1305 (bits 13 to 17) specifies a register in acorresponding register file as the first source operand.

The opcode field 1306 (bits 3 to 12) for all instructions (andadditionally bits 28 to 31 for unconditional instructions) specifies thetype of instruction and designates appropriate instruction options. Thisincludes unambiguous designation of the functional unit used andoperation performed. A detailed explanation of the opcode is beyond thescope of this invention except for the instruction options detailedbelow.

The e bit 1307 (bit 2) is only used for immediate constant instructionswhere the constant may be extended. If e=1, then the immediate constantis extended in a manner detailed below. If e=0, then the immediateconstant is not extended. In that case the immediate constant isspecified by the src2/cst field 1304 (bits 18 to 22). Note that this ebit 1307 is used for only some instructions. Accordingly, with propercoding this e bit 1307 may be omitted from instructions which do notneed it and this bit used as an additional opcode bit.

The s bit 1308 (bit 1) designates scalar datapath side A 115 or vectordatapath side B 116. If s=0, then scalar datapath side A 115 isselected. This limits the functional unit to L1 unit 221, S1 unit 222,M1 unit 223, N1 unit 224, D1 unit 225 and D2 unit 226 and thecorresponding register files illustrated in FIG. 2 . Similarly, s=1selects vector datapath side B 116 limiting the functional unit to L2unit 241, S2 unit 242, M2 unit 243, N2 unit 244, P unit 246 and thecorresponding register file illustrated in FIG. 2 .

The p bit 1309 (bit 0) marks the execute packets. The p-bit determineswhether the instruction executes in parallel with the followinginstruction. The p-bits are scanned from lower to higher address. If p=1for the current instruction, then the next instruction executes inparallel with the current instruction. If p=0 for the currentinstruction, then the next instruction executes in the cycle after thecurrent instruction. All instructions executing in parallel constitutean execute packet. An execute packet can contain up to twelveinstructions. Each instruction in an execute packet must use a differentfunctional unit.

There are two different condition code extension slots. Each executepacket can contain one each of these unique 32-bit condition codeextension slots which contains the 4-bit creg/z fields for theinstructions in the same execute packet. FIG. 14 illustrates the codingfor condition code extension slot 0 and FIG. 15 illustrates the codingfor condition code extension slot 1.

FIG. 14 illustrates the coding for condition code extension slot 0 1400having 32 bits. Field 1401 (bits 28 to 31) specify 4 creg/z bitsassigned to the L1 unit 221 instruction in the same execute packet.Field 1402 (bits 27 to 24) specify 4 creg/z bits assigned to the L2 unit241 instruction in the same execute packet. Field 1403 (bits 19 to 23)specify 4 creg/z bits assigned to the S1 unit 222 instruction in thesame execute packet. Field 1404 (bits 16 to 19) specify 4 creg/z bitsassigned to the S2 unit 242 instruction in the same execute packet.Field 1405 (bits 12 to 15) specify 4 creg/z bits assigned to the D1 unit225 instruction in the same execute packet. Field 1406 (bits 8 to 11)specify 4 creg/z bits assigned to the D2 unit 226 instruction in thesame execute packet. Field 1407 (bits 6 and 7) is unused/reserved. Field1408 (bits 0 to 5) are coded a set of unique bits (CCEX0) to identifythe condition code extension slot 0. Once this unique ID of conditioncode extension slot 0 is detected, the corresponding creg/z bits areemployed to control conditional execution of any L1 unit 221, L2 unit241, S1 unit 222, S2 unit 242, D1 unit 225 and D2 unit 226 instructionin the same execution packet. These creg/z bits are interpreted as shownin Table 1. If the corresponding instruction is conditional (includescreg/z bits) the corresponding bits in the condition code extension slot0 override the condition code bits in the instruction. Note that noexecution packet can have more than one instruction directed to aparticular execution unit. No execute packet of instructions can containmore than one condition code extension slot 0. Thus the mapping ofcreg/z bits to functional unit instruction is unambiguous. Setting thecreg/z bits equal to “0000” makes the instruction unconditional. Thus aproperly coded condition code extension slot 0 can make somecorresponding instructions conditional and some unconditional.

FIG. 15 illustrates the coding for condition code extension slot 1 1500having 32 bits. Field 1501 (bits 28 to 31) specify 4 creg/z bitsassigned to the M1 unit 223 instruction in the same execute packet.Field 1502 (bits 27 to 24) specify 4 creg/z bits assigned to the M2 unit243 instruction in the same execute packet. Field 1503 (bits 19 to 23)specify 4 creg/z bits assigned to the C unit 245 instruction in the sameexecute packet. Field 1504 (bits 16 to 19) specify 4 creg/z bitsassigned to the N1 unit 224 instruction in the same execute packet.Field 1505 (bits 12 to 15) specify 4 creg/z bits assigned to the N2 unit244 instruction in the same execute packet. Field 1506 (bits 6 to 11) isunused/reserved. Field 1507 (bits 0 to 5) are coded a set of unique bits(CCEX1) to identify the condition code extension slot 1. Once thisunique ID of condition code extension slot 1 is detected, thecorresponding creg/z bits are employed to control conditional executionof any M1 unit 223, M2 unit 243, C unit 245, N1 unit 224 and N2 unit 244instruction in the same execution packet. These creg/z bits areinterpreted as shown in Table 1. If the corresponding instruction isconditional (includes creg/z bits) the corresponding bits in thecondition code extension slot 1 override the condition code bits in theinstruction. Note that no execution packet can have more than oneinstruction directed to a particular execution unit. No execute packetof instructions can contain more than one condition code extensionslot 1. Thus the mapping of creg/z bits to functional unit instructionis unambiguous. Setting the creg/z bits equal to “0000” makes theinstruction unconditional. Thus a properly coded condition codeextension slot 1 can make some instructions conditional and someunconditional.

It is feasible for both condition code extension slot 0 and conditioncode extension slot 1 to include a p bit to define an execute packet asdescribed above in conjunction with FIG. 13 . In the preferredembodiment, as illustrated in FIGS. 14 and 15 , code extension slot 0and condition code extension slot 1 preferably have bit 0 (p bit) alwaysencoded as 1. Thus neither condition code extension slot 0 not conditioncode extension slot 1 can be in the last instruction slot of an executepacket.

There are two different constant extension slots. Each execute packetcan contain one each of these unique 32-bit constant extension slotswhich contains 27 bits to be concatenated as high order bits with the5-bit constant field 1305 to form a 32-bit constant. As noted in theinstruction coding description above only some instructions define thesrc2/cst field 1304 as a constant rather than a source registeridentifier. At least some of those instructions may employ a constantextension slot to extend this constant to 32 bits.

FIG. 16 illustrates the fields of constant extension slot 0. Eachexecute packet may include one instance of constant extension slot 0 andone instance of constant extension slot 1. FIG. 16 illustrates thatconstant extension slot 0 1600 includes two fields. Field 1601 (bits 5to 31) constitute the most significant 27 bits of an extended 32-bitconstant including the target instruction scr2/cst field 1304 as thefive least significant bits. Field 1602 (bits 0 to 4) are coded a set ofunique bits (CSTX0) to identify the constant extension slot 0. In thepreferred embodiment constant extension slot 0 1600 can only be used toextend the constant of one of an L1 unit 221 instruction, data in a D1unit 225 instruction, an S2 unit 242 instruction, an offset in a D2 unit226 instruction, an M2 unit 243 instruction, an N2 unit 244 instruction,a branch instruction, or a C unit 245 instruction in the same executepacket. Constant extension slot 1 is similar to constant extension slot0 except that bits 0 to 4 are coded a set of unique bits (CSTX1) toidentify the constant extension slot 1. In the preferred embodimentconstant extension slot 1 can only be used to extend the constant of oneof an L2 unit 241 instruction, data in a D2 unit 226 instruction, an S1unit 222 instruction, an offset in a D1 unit 225 instruction, an M1 unit223 instruction or an N1 unit 224 instruction in the same executepacket.

Constant extension slot 0 and constant extension slot 1 are used asfollows. The target instruction must be of the type permitting constantspecification. As known in the art this is implemented by replacing oneinput operand register specification field with the least significantbits of the constant as described above with respect to scr2/cst field1304. Instruction decoder 113 determines this case, known as animmediate field, from the instruction opcode bits. The targetinstruction also includes one constant extension bit (e bit 1307)dedicated to signaling whether the specified constant is not extended(preferably constant extension bit=0) or the constant is extended(preferably constant extension bit=1). If instruction decoder 113detects a constant extension slot 0 or a constant extension slot 1, itfurther checks the other instructions within that execute packet for aninstruction corresponding to the detected constant extension slot. Aconstant extension is made only if one corresponding instruction has aconstant extension bit (e bit 1307) equal to 1.

FIG. 17 is a partial block diagram 1700 illustrating constant extension.FIG. 17 assumes that instruction decoder 113 detects a constantextension slot and a corresponding instruction in the same executepacket. Instruction decoder 113 supplies the 27 extension bits from theconstant extension slot (bit field 1601) and the 5 constant bits (bitfield 1305) from the corresponding instruction to concatenator 1701.Concatenator 1701 forms a single 32-bit word from these two parts. Inthe preferred embodiment the 27 extension bits from the constantextension slot (bit field 1601) are the most significant bits and the 5constant bits (bit field 1305) are the least significant bits. Thiscombined 32-bit word is supplied to one input of multiplexer 1702. The 5constant bits from the corresponding instruction field 1305 supply asecond input to multiplexer 1702. Selection of multiplexer 1702 iscontrolled by the status of the constant extension bit. If the constantextension bit (e bit 1307) is 1 (extended), multiplexer 1702 selects theconcatenated 32-bit input. If the constant extension bit is 0 (notextended), multiplexer 1702 selects the 5 constant bits from thecorresponding instruction field 1305. Multiplexer 1702 supplies thisoutput to an input of sign extension unit 1703.

Sign extension unit 1703 forms the final operand value from the inputfrom multiplexer 1703. Sign extension unit 1703 receives control inputsScalar/Vector and Data Size. The Scalar/Vector input indicates whetherthe corresponding instruction is a scalar instruction or a vectorinstruction. The functional units of data path side A 115 (L1 unit 221,S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225 and D2 unit 226) canonly perform scalar instructions. Any instruction directed to one ofthese functional units is a scalar instruction. Data path side Bfunctional units L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244 andC unit 245 may perform scalar instructions or vector instructions.Instruction decoder 113 determines whether the instruction is a scalarinstruction or a vector instruction from the opcode bits. P unit 246 mayonly perform scalar instructions. The Data Size may be 8 bits (byte B),16 bits (half-word H), 32 bits (word W) or 64 bits (double word D).

Table 2 lists the operation of sign extension unit 1703 for the variousoptions.

TABLE 2 Instruction Operand Constant Type Size Length Action ScalarB/H/W/D  5 bits Sign extend to 64 bits Scalar B/H/W/D 32 bits Signextend to 64 bits Vector B/H/W/D  5 bits Sign extend to operand size andreplicate across whole vector Vector B/H/W 32 bits Replicate 32-bitconstant across each 32-bit (W) lane Vector D 32 bits Sign extend to 64bits and replicate across each 64-bit (D) lane

It is feasible for both constant extension slot 0 and constant extensionslot 1 to include a p bit to define an execute packet as described abovein conjunction with FIG. 13 . In the preferred embodiment, as in thecase of the condition code extension slots, constant extension slot 0and constant extension slot 1 preferably have bit 0 (p bit) alwaysencoded as 1. Thus neither constant extension slot 0 nor constantextension slot 1 can be in the last instruction slot of an executepacket.

It is technically feasible for an execute packet to include a constantextension slot 0 or 1 and more than one corresponding instruction markedconstant extended (e bit=1). For constant extension slot 0 this wouldmean more than one of an L1 unit 221 instruction, data in a D1 unit 225instruction, an S2 unit 242 instruction, an offset in a D2 unit 226instruction, an M2 unit 243 instruction or an N2 unit 244 instruction inan execute packet have an e bit of 1. For constant extension slot 1 thiswould mean more than one of an L2 unit 241 instruction, data in a D2unit 226 instruction, an S1 unit 222 instruction, an offset in a D1 unit225 instruction, an M1 unit 223 instruction or an N1 unit 224instruction in an execute packet have an e bit of 1. Supplying the sameconstant extension to more than one instruction is not expected to be auseful function. Accordingly, in one embodiment instruction decoder 113may determine this case an invalid operation and not supported.Alternately, this combination may be supported with extension bits ofthe constant extension slot applied to each corresponding functionalunit instruction marked constant extended.

L1 unit 221, S1 unit 222, L2 unit 241, S2 unit 242 and C unit 245 oftenoperate in a single instruction multiple data (SIMD) mode. In this SIMDmode the same instruction is applied to packed data from the twooperands. Each operand holds plural data elements disposed inpredetermined slots. SIMD operation is enabled by carry control at thedata boundaries. Such carry control enables operations on varying datawidths.

FIG. 18 illustrates the carry control. AND gate 1801 receives the carryoutput of bit N within the operand wide arithmetic logic unit (64 bitsfor scalar datapath side A 115 functional units and 512 bits for vectordatapath side B 116 functional units). AND gate 1801 also receives acarry control signal which will be further explained below. The outputof AND gate 1801 is supplied to the carry input of bit N+1 of theoperand wide arithmetic logic unit. AND gates such as AND gate 1801 aredisposed between every pair of bits at a possible data boundary. Forexample, for 8-bit data such an AND gate will be between bits 7 and 8,bits 15 and 16, bits 23 and 24, etc. Each such AND gate receives acorresponding carry control signal. If the data size is of the minimum,then each carry control signal is 0, effectively blocking carrytransmission between the adjacent bits. The corresponding carry controlsignal is 1 if the selected data size requires both arithmetic logicunit sections. Table 3 below shows example carry control signals for thecase of a 512 bit wide operand such as used by vector datapath side B116 functional units which may be divided into sections of 8 bits, 16bits, 32 bits, 64 bits, 128 bits or 256 bits. In Table 3 the upper 32bits control the upper bits (bits 128 to 511) carries and the lower 32bits control the lower bits (bits 0 to 127) carries. No control of thecarry output of the most significant bit is needed, thus only 63 carrycontrol signals are required.

TABLE 3 Data Size Carry Control Signals  8 bits (B) −000 0000 0000 00000000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000  16 bits (H)−101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 01010101 0101  32 bits (W) −111 0111 0111 0111 0111 0111 0111 0111 0111 01110111 0111 0111 0111 0111 0111  64 bits (D) −111 1111 0111 1111 0111 11110111 1111 0111 1111 0111 1111 0111 1111 0111 1111 128 bits −111 11111111 1111 0111 1111 1111 1111 0111 1111 1111 1111 0111 1111 1111 1111256 bits −111 1111 1111 1111 1111 1111 1111 1111 0111 1111 1111 11111111 1111 1111 1111

It is typical in the art to operate on data sizes that are integralpowers of 2 (2^(N)). However, this carry control technique is notlimited to integral powers of 2. One skilled in the art would understandhow to apply this technique to other data sizes and other operandwidths.

In the preferred embodiment at least L unit 241 and S unit 242 employtwo types of SIMD instructions using registers in predicate registerfile 234. In the preferred embodiment all these SIMD vector predicateinstructions operate on an instruction specified data size. The datasizes may include byte (8 bit) data, half word (16 bit) data, word (32bit) data, double word (64 bit) data, quad word (128 bit) data and halfvector (256 bit) data. In the first of these instruction types, thefunctional unit (L unit 241 or S unit 242) performs a SIMD comparison onpacked data in two general data registers and supplies results to apredicate data register. The instruction specifies a data size, the twogeneral data register operands and the destination predicate register.In the preferred embodiment each predicate data register includes onebit corresponding to each minimal data size portion of the general dataregisters. In the current embodiment the general data registers are 512bits (64 bytes) and the predicate data registers are 64 bits (8 bytes).Each bit of a predicate data register corresponds to 8 bits of a generaldata register. The comparison is performed on a specified data size (8,16, 32, 64, 128 or 256 bits). If the comparison is true then thefunctional unit supplies 1's to all predicate register bitscorresponding the that data size portion. If the comparison is falsethen the functional unit supplies 0's to all predicate register bitscorresponding to that data size portion. In the preferred embodiment theenabled comparison operations include: less than; greater than; andequal to.

In the second of these instruction types, the functional unit (L unit241 or S unit 242) separately performs a first SIMD operation or asecond SIMD operation on packed data in general data registers basedupon the state of data in a predicate data register. The instructionspecifies a data size, one or two general data register operands, acontrolling predicate register and a general data register destination.For example a functional unit may select, for each data sized portion oftwo vector operands, a first data element of a first operand or a seconddata element of a second operand dependent upon the 1/0 state ofcorrespond bits in the predicate data register to store in thedestination register. In a second example, the data elements of a singlevector operand may be saved to memory or not saved dependent upon thedata of the corresponding bits of the predicate register.

The operations of P unit 245 permit a variety of compound vector SIMDoperations based upon more than one vector comparison. For example arange determination can be made using two comparisons. In a SIMDoperation a candidate vector is compared with a first vector referencehaving the minimum of the range packed within a first data register. Thegreater than result is scalar data with bits corresponding to the SIMDdata width set to 0 or 1 depending upon the SIMD comparison. This isstored in a first predicate data register. A second SIMD comparison ofthe candidate vector is made with a second reference vector having themaximum of the range packed within a second data register producesanother scalar with less than results stored in a second predicateregister. The P unit then ANDs the first and second predicate registers.The AND result indicates whether each SIMD data part of the candidatevector is within range or out of range. A P unit BITCNT instruction ofthe AND result could produce a count of the data elements within thecomparison range. The P unit NEG function may be used to convert: a lessthan comparison result to a greater than or equal comparison result; agreater than comparison result to a less than or equal to comparisonresult; or an equal to comparison result to a not equal to comparisonresult.

FIG. 19 illustrates a conceptual view of the streaming engines of thisinvention. FIG. 19 illustrates the process of a single stream. Streamingengine 1900 includes stream address generator 1901. Stream addressgenerator 1901 sequentially generates addresses of the elements of thestream and supplies these element addresses to system memory 1910.Memory 1910 recalls data stored at the element addresses (data elements)and supplies these data elements to data first-in-first-out (FIFO)memory 1902. Data FIFO 1902 provides buffering between memory 1910 andCPU 1920. Data formatter 1903 receives the data elements from data FIFOmemory 1902 and provides data formatting according to the streamdefinition. This process will be described below. Streaming engine 1900supplies the formatted data elements from data formatter 1903 to the CPU1920. The program on CPU 1920 consumes the data and generates an output.

Stream elements typically reside in normal memory. The memory itselfimposes no particular structure upon the stream. Programs define streamsand therefore impose structure, by specifying the following streamattributes: address of the first element of the stream; size and type ofthe elements in the stream; formatting for data in the stream; and theaddress sequence associated with the stream.

The streaming engine defines an address sequence for elements of thestream in terms of a pointer walking through memory. A multiple-levelnested loop controls the path the pointer takes. An iteration count fora loop level indicates the number of times that level repeats. Adimension gives the distance between pointer positions of that looplevel.

In a basic forward stream the innermost loop always consumes physicallycontiguous elements from memory. The implicit dimension of thisinnermost loop is 1 element. The pointer itself moves from element toelement in consecutive, increasing order. In each level outside theinner loop, that loop moves the pointer to a new location based on thesize of that loop level's dimension.

This form of addressing allows programs to specify regular paths throughmemory in a small number of parameters. Table 4 lists the addressingparameters of a basic stream.

TABLE 4 Parameter Definition ELEM_BYTES Size of each element in bytesICNT0 Number of iterations for the innermost loop level 0. At loop level0 all elements are physically contiguous DIM0 is ELEM_BYTES ICNT1 Numberof iterations for loop level 1 DIM1 Number of bytes between the startingpoints for consecutive iterations of loop level 1 ICNT2 Number ofiterations for loop level 2 DIM2 Number of bytes between the startingpoints for consecutive iterations of loop level 2 ICNT3 Number ofiterations for loop level 3 DIM3 Number of bytes between the startingpoints for consecutive iterations of loop level 3 ICNT4 Number ofiterations for loop level 4 DIM4 Number of bytes between the startingpoints for consecutive iterations of loop level 4 ICNT5 Number ofiterations for loop level 5 DIM5 Number of bytes between the startingpoints for consecutive iterations of loop level 5

In accordance with the preferred embodiment of this invention ELEM_BYTESranges from 1 to 64 bytes as shown in Table 5.

TABLE 5 ELEM_BYTES Stream Element Length 000  1 byte 001  2 bytes 010  4bytes 011  8 bytes 100 16 bytes 101 32 bytes 110 64 bytes 111 Reserved

The definition above maps consecutive elements of the stream toincreasing addresses in memory. This works well for most algorithms butnot all. Some algorithms are better served by reading elements indecreasing memory addresses, reverse stream addressing. For example, adiscrete convolution computes vector dot-products, as per the formula:

${\left( {f,g} \right)\lbrack t\rbrack} = {\sum\limits_{x = {- \infty}}^{\infty}{{f\lbrack x\rbrack}{g\left\lbrack {t - x} \right\rbrack}}}$

In most DSP code, f[] and g[] represent arrays in memory. For eachoutput, the algorithm reads f[] in the forward direction, but reads g[]in the reverse direction. Practical filters limit the range of indicesfor [x] and [t-x] to a finite number elements. To support this pattern,the streaming engine supports reading elements in decreasing addressorder.

Matrix multiplication presents a unique problem to the streaming engine.Each element in the matrix product is a vector dot product between a rowfrom the first matrix and a column from the second. Programs typicallystore matrices all in row-major or column-major order. Row-major orderstores all the elements of a single row contiguously in memory.Column-major order stores all elements of a single column contiguouslyin memory. Matrices typically get stored in the same order as thedefault array order for the language. As a result, only one of the twomatrices in a matrix multiplication map on to the streaming engine's2-dimensional stream definition. In a typical example a first indexsteps through columns on array first array but rows on second array.This problem is not unique to the streaming engine. Matrixmultiplication's access pattern fits poorly with most general-purposememory hierarchies. Some software libraries transposed one of the twomatrices, so that both get accessed row-wise (or column-wise) duringmultiplication. The streaming engine supports implicit matrixtransposition with transposed streams. Transposed streams avoid the costof explicitly transforming the data in memory. Instead of accessing datain strictly consecutive-element order, the streaming engine effectivelyinterchanges the inner two loop dimensions in its traversal order,fetching elements along the second dimension into contiguous vectorlanes.

This algorithm works, but is impractical to implement for small elementsizes. Some algorithms work on matrix tiles which are multiple columnsand rows together. Therefore, the streaming engine defines a separatetransposition granularity. The hardware imposes a minimum granularity.The transpose granularity must also be at least as large as the elementsize. Transposition granularity causes the streaming engine to fetch oneor more consecutive elements from dimension 0 before moving alongdimension 1. When the granularity equals the element size, this resultsin fetching a single column from a row-major array. Otherwise, thegranularity specifies fetching 2, 4 or more columns at a time from arow-major array. This is also applicable for column-major layout byexchanging row and column in the description. A parameter GRANULEindicates the transposition granularity in bytes.

Another common matrix multiplication technique exchanges the innermosttwo loops of the matrix multiply. The resulting inner loop no longerreads down the column of one matrix while reading across the row ofanother. For example the algorithm may hoist one term outside the innerloop, replacing it with the scalar value. On a vector machine, theinnermost loop can be implements very efficiently with a singlescalar-by-vector multiply followed by a vector add. The centralprocessing unit core 110 of this invention lacks a scalar-by-vectormultiply. Programs must instead duplicate the scalar value across thelength of the vector and use a vector-by-vector multiply. The streamingengine of this invention directly supports this and related use modelswith an element duplication mode. In this mode, the streaming enginereads a granule smaller than the full vector size and replicates thatgranule to fill the next vector output.

The streaming engine treats each complex number as a single element withtwo sub-elements that give the real and imaginary (rectangular) ormagnitude and angle (polar) portions of the complex number. Not allprograms or peripherals agree what order these sub-elements shouldappear in memory. Therefore, the streaming engine offers the ability toswap the two sub-elements of a complex number with no cost. This featureswaps the halves of an element without interpreting the contents of theelement and can be used to swap pairs of sub-elements of any type, notjust complex numbers.

Algorithms generally prefer to work at high precision, but highprecision values require more storage and bandwidth than lower precisionvalues. Commonly, programs will store data in memory at low precision,promote those values to a higher precision for calculation and thendemote the values to lower precision for storage. The streaming enginesupports this directly by allowing algorithms to specify one level oftype promotion. In the preferred embodiment of this invention everysub-element may be promoted to a larger type size with either sign orzero extension for integer types. It is also feasible that the streamingengine may support floating point promotion, promoting 16-bit and 32-bitfloating point values to 32-bit and 64-bit formats, respectively.

The streaming engine defines a stream as a discrete sequence of dataelements, the central processing unit core 110 consumes data elementspacked contiguously in vectors. Vectors resemble streams in as much asthey contain multiple homogeneous elements with some implicit sequence.Because the streaming engine reads streams, but the central processingunit core 110 consumes vectors, the streaming engine must map streamsonto vectors in a consistent way.

Vectors consist of equal-sized lanes, each lane containing asub-element. The central processing unit core 110 designates therightmost lane of the vector as lane 0, regardless of device's currentendian mode. Lane numbers increase right-to-left. The actual number oflanes within a vector varies depending on the length of the vector andthe data size of the sub-element.

FIG. 20 illustrates the sequence of the formatting operations offormatter 1903. Formatter 1903 includes three sections: input section2010; formatting section 2020; and output section 2030. Input section2010 receives the data recalled from system memory 1910 as accessed bystream address generator 1901. This data could be via linear fetchstream 2011 or transposed fetch stream 2012.

Formatting section 2020 includes various formatting blocks. Theformatting performed by formatter 1903 by these blocks will be furtherdescribed below. Complex swap block 2021 optionally swaps twosub-elements forming a complex number element. Type promotion block 2022optionally promotes each data element into a larger data size. Promotionincludes zero extension for unsigned integers and sign extension forsigned integers. Decimation block 2023 optionally decimates the dataelements. In the preferred embodiment decimation can be 2:1 retainingevery other data element of 4:1 retaining every fourth data element.Element duplication block 2024 optionally duplicates individual dataelements. In the preferred embodiment this data element duplication isan integer power of 2 (2^(N), when N is an integer) including 2x, 4x,8x, 16x, 32x and 64x. In the preferred embodiment data duplication canextend over plural destination vectors. Vector length masking/groupduplication block 2025 has two primary functions. An independentlyspecified vector length VECLEN controls the data elements supplied toeach output data vector. When group duplication is off, excess lanes inthe output data vector are zero filled and these lanes are markedinvalid. When group duplication is on, input data elements of thespecified vector length are duplicated to fill the output data vector.

Output section 2030 holds the data for output to the correspondingfunctional units. Register and buffer for CPU 2031 stores a formattedvector of data to be used as an operand by the functional units ofcentral processing unit core 110.

FIG. 21 illustrates a first example of lane allocation in a vector.Vector 2100 is divided into 8 64-bit lanes (8×64 bits=512 bits thevector length). Lane 0 includes bits 0 to 63; line 1 includes bits 64 to127; lane 2 includes bits 128 to 191; lane 3 includes bits 192 to 255,lane 4 includes bits 256 to 319, lane 5 includes bits 320 to 383, lane 6includes bits 384 to 447 and lane 7 includes bits 448 to 511.

FIG. 22 illustrates a second example of lane allocation in a vector.Vector 2210 is divided into 16 32-bit lanes (16×32 bits=512 bits thevector length). Lane 0 includes bits 0 to 31; line 1 includes bits 32 to63; lane 2 includes bits 64 to 95; lane 3 includes bits 96 to 127; lane4 includes bits 128 to 159; lane 5 includes bits 160 to 191; lane 6includes bits 192 to 223; lane 7 includes bits 224 to 255; lane 8includes bits 256 to 287; line 9 occupied bits 288 to 319; lane 10includes bits 320 to 351; lane 11 includes bits 352 to 383; lane 12includes bits 384 to 415; lane 13 includes bits 416 to 447; lane 14includes bits 448 to 479; and lane 15 includes bits 480 to 511.

The streaming engine maps the innermost stream dimension directly tovector lanes. It maps earlier elements within that dimension to lowerlane numbers and later elements to higher lane numbers. This is trueregardless of whether this particular stream advances in increasing ordecreasing address order. Whatever order the stream defines, thestreaming engine deposits elements in vectors in increasing-lane order.For non-complex data, it places the first element in lane 0 of the firstvector central processing unit core 110 fetches, the second in lane 1,and so on. For complex data, the streaming engine places the firstelement in lanes 0 and 1, second in lanes 2 and 3, and so on.Sub-elements within an element retain the same relative orderingregardless of the stream direction. For non-swapped complex elements,this places the sub-elements with the lower address of each pair in theeven numbered lanes, and the sub-elements with the higher address ofeach pair in the odd numbered lanes. Swapped complex elements reversethis mapping.

The streaming engine fills each vector central processing unit core 110fetches with as many elements as it can from the innermost streamdimension. If the innermost dimension is not a multiple of the vectorlength, the streaming engine pads that dimension out to the vectorlength with zeros. As noted below the streaming engine will also markthese lanes invalid. Thus for higher-dimension streams, the firstelement from each iteration of an outer dimension arrives in lane 0 of avector. The streaming engine always maps the innermost dimension toconsecutive lanes in a vector. For transposed streams, the innermostdimension consists of groups of sub-elements along dimension 1, notdimension 0, as transposition exchanges these two dimensions.

Two dimensional streams exhibit greater variety as compared to onedimensional streams. A basic two dimensional stream extracts a smallerrectangle from a larger rectangle. A transposed 2-D stream reads arectangle column-wise instead of row-wise. A looping stream, where thesecond dimension overlaps first executes a finite impulse response (FIR)filter taps which loops repeatedly or FIR filter samples which provide asliding window of input samples.

FIG. 23 illustrates a basic two dimensional stream. The inner twodimensions, represented by ELEM_BYTES, ICNT0,DIM1 and ICNT1 givesufficient flexibility to describe extracting a smaller rectangle 2320having dimensions 2321 and 2322 from a larger rectangle 2310 havingdimensions 2311 and 2312. In this example rectangle 2320 is a 9 by 13rectangle of 64-bit values and rectangle 2310 is a larger 11 by 19rectangle. The following stream parameters define this stream:

-   -   ICNT0=9    -   ELEM_BYTES=8    -   ICNT1=13    -   DIM1=88 (11 times 8)

Thus the iteration count in the 0 dimension 2321 is 9. The iterationcount in the 1 direction 2322 is 13. Note that the ELEM_BYTES onlyscales the innermost dimension. The first dimension has ICNT0 elementsof size ELEM_BYTES. The stream address generator does not scale theouter dimensions. Therefore, DIM1=88, which is 11 elements scaled by 8bytes per element.

FIG. 24 illustrates the order of elements within this example stream.The streaming engine fetches elements for the stream in the orderillustrated in order 2400. The first 9 elements come from the first rowof rectangle 2320, left-to-right in hops 1 to 8. The 10th through 24thelements comes from the second row, and so on. When the stream movesfrom the 9th element to the 10th element (hop 9 in FIG. 24 ), thestreaming engine computes the new location based on the pointer'sposition at the start of the inner loop, not where the pointer ended upat the end of the first dimension. This makes DIM1 independent ofELEM_BYTES and ICNT0. DIM1 always represents the distance between thefirst bytes of each consecutive row.

Transposed streams access along dimension 1 before dimension 0. Thefollowing examples illustrate a couple transposed streams, varying thetransposition granularity. FIG. 25 illustrates extracting a smallerrectangle 2520 (12×8) having dimensions 2521 and 2522 from a largerrectangle 2510 (14×13) having dimensions 2511 and 2512. In FIG. 25ELEM_BYTES equals 2.

FIG. 26 illustrates how the streaming engine would fetch the stream ofthis example with a transposition granularity of 4 bytes. Fetch pattern2600 fetches pairs of elements from each row (because the granularity of4 is twice the ELEM_BYTES of 2), but otherwise moves down the columns.Once it reaches the bottom of a pair of columns, it repeats this patternwith the next pair of columns.

FIG. 27 illustrates how the streaming engine would fetch the stream ofthis example with a transposition granularity of 8 bytes. The overallstructure remains the same. The streaming engine fetches 4 elements fromeach row (because the granularity of 8 is four times the ELEM_BYTES of2) before moving to the next row in the column as shown in fetch pattern2700.

The streams examined so far read each element from memory exactly once.A stream can read a given element from memory multiple times, in effectlooping over a piece of memory. FIR filters exhibit two common loopingpatterns. FIRs re-read the same filter taps for each output. FIRs alsoread input samples from a sliding window. Two consecutive outputs willneed inputs from two overlapping windows.

FIG. 28 illustrates the details of streaming engine 2800. Streamingengine 2800 contains three major sections: Stream 0 2810; Stream 1 2820;and Shared L2 Interfaces 2830. Stream 0 2810 and Stream 1 2820 bothcontain identical hardware that operates in parallel. Stream 0 2810 andStream 1 2820 both share L2 interfaces 2830. Each stream 2810 and 2820provides central processing unit core 110 with up to 512 bits/cycle,every cycle. The streaming engine architecture enables this through itsdedicated stream paths and shared dual L2 interfaces.

Each streaming engine 2800 includes a dedicated 6-dimensional streamaddress generator 2811/2821 that can each generate one new non-alignedrequest per cycle. Address generators 2811/2821 output 512-bit alignedaddresses that overlap the elements in the sequence defined by thestream parameters. This will be further described below.

Each address generator 2811/2811 connects to a dedicated micro tablelook-aside buffer (pTLB) 2812/2822. The pTLB 2812/2822 converts a single48-bit virtual address to a 44-bit physical address each cycle. EachpTLB 2812/2822 has 8 entries, covering a minimum of 32 kB with 4 kBpages or a maximum of 16 MB with 2 MB pages. Each address generator2811/2821 generates 2 addresses per cycle. The pTLB 2812/2822 onlytranslates 1 address per cycle. To maintain throughput, streaming engine2800 takes advantage of the fact that most stream references will bewithin the same 4 kB page. Thus the address translation does not modifybits 0 to 11 of the address. If aout0 and aout1 line in the same 4 kBpage (aout0[47:12] are the same aout1[47:12]), then the pTLB 2812/2822only translates aout0 and reuses the translation for the upper bits ofboth addresses.

Translated addresses are queued in command queue 2813/2823. Theseaddresses are aligned with information from the corresponding StorageAllocation and Tracking block 2814/2824. Streaming engine 2800 does notexplicitly manage pTLB 2812/2822. The system memory management unit(MMU) invalidates pTLBs as necessary during context switches.

Storage Allocation and Tracking 2814/2824 manages the stream's internalstorage, discovering data reuse and tracking the lifetime of each pieceof data. This will be further described below.

Reference queue 2815/2825 stores the sequence of references generated bythe corresponding address generator 2811/2821. This information drivesthe data formatting network so that it can present data to centralprocessing unit core 110 in the correct order. Each entry in referencequeue 2815/2825 contains the information necessary to read data out ofthe data store and align it for central processing unit core 110.Reference queue 2815/2825 maintains the following information listed inTable 6 in each slot:

TABLE 6 Data Slot Low Slot number for the lower half of data associatedwith aout0 Data Slot High Slot number for the upper half of dataassociated with aout1 Rotation Number of bytes to rotate data to alignnext element with lane 0 Length Number of valid bytes in this reference

Storage allocation and tracking 2814/2824 inserts references inreference queue 2815/2825 as address generator 2811/2821 generates newaddresses. Storage allocation and tracking 2814/2824 removes referencesfrom reference queue 2815/2825 when the data becomes available and thereis room in the stream head registers. As storage allocation and tracking2814/2824 removes slot references from reference queue 2815/2825 andformats data, it checks whether the references represent the lastreference to the corresponding slots. Storage allocation and tracking2814/2824 compares reference queue 2815/2825 removal pointer against theslot's recorded Last Reference. If they match, then storage allocationand tracking 2814/2824 marks the slot inactive once it's done with thedata.

Streaming engine 2800 has data storage 2816/2826 for an arbitrary numberof elements. Deep buffering allows the streaming engine to fetch farahead in the stream, hiding memory system latency. The right amount ofbuffering might vary from product generation to generation. In thecurrent preferred embodiment streaming engine 2800 dedicates 32 slots toeach stream. Each slot holds 64 bytes of data.

Butterfly network 2817/2827 consists of a 7 stage butterfly network.Butterfly network 2817/2827 receives 128 bytes of input and generates 64bytes of output. The first stage of the butterfly is actually ahalf-stage. It collects bytes from both slots that match a non-alignedfetch and merges them into a single, rotated 64-byte array. Theremaining 6 stages form a standard butterfly network.

Butterfly network 2817/2827 performs the following operations: rotatesthe next element down to byte lane 0; promotes data types by a power of2, if requested; swaps real and imaginary components of complex numbers,if requested; converts big endian to little endian if central processingunit core 110 is presently in big endian mode. The user specifieselement size, type promotion and real/imaginary swap as part of thestream's parameters.

Streaming engine 2800 attempts to fetch and format data ahead of centralprocessing unit core 110's demand for it, so that it can maintain fullthroughput. Stream head registers 2818/2828 provide a small amount ofbuffering so that the process remains fully pipelined. Holding registers2818/2828 are not directly architecturally visible, except for the factthat streaming engine 2800 provides full throughput. Each stream alsohas a stream valid register 2819/2829. Valid registers 2819/2829indicate which elements in the corresponding stream head registers2818/2828 are valid.

The two streams 2810/2820 share a pair of independent L2 interfaces2830: L2 Interface A (IFA) 2833 and L2 Interface B (IFB) 2834. Each L2interface provides 512 bits/cycle throughput direct to the L2 controllerfor an aggregate bandwidth of 1024 bits/cycle. The L2 interfaces use thecredit-based multicore bus architecture (MBA) protocol. The L2controller assigns each interface its own pool of command credits. Thepool should have sufficient credits so that each interface can sendsufficient requests to achieve full read-return bandwidth when readingL2 RAM, L2 cache and multicore shared memory controller (MSMC) memory(described below).

To maximize performance, both streams can use both L2 interfaces,allowing a single stream to send a peak command rate of 2requests/cycle. Each interface prefers one stream over the other, butthis preference changes dynamically from request to request. IFA 2833and IFB 2834 always prefer opposite streams, when IFA 2833 prefersStream 0, IFB 2834 prefers Stream 1 and vice versa.

Arbiter 2831/2832 ahead of each interface 2833/2834 applies thefollowing basic protocol on every cycle it has credits available.Arbiter 2831/2832 checks if the preferred stream has a command ready tosend. If so, arbiter 2831/2832 chooses that command. Arbiter 2831/2832next checks if an alternate stream has at least two requests ready tosend, or one command and no credits. If so, arbiter 2831/2832 pulls acommand from the alternate stream. If either interface issues a command,the notion of preferred and alternate streams swap for the next request.Using this simple algorithm, the two interfaces dispatch requests asquickly as possible while retaining fairness between the two streams.The first rule ensures that each stream can send a request on everycycle that has available credits. The second rule provides a mechanismfor one stream to borrow the other's interface when the second interfaceis idle. The third rule spreads the bandwidth demand for each streamacross both interfaces, ensuring neither interface becomes a bottleneckby itself.

Coarse Grain Rotator 2835/2836 enables streaming engine 2800 to supporta transposed matrix addressing mode. In this mode, streaming engine 2800interchanges the two innermost dimensions of its multidimensional loop.This accesses an array column-wise rather than row-wise. Rotator2835/2836 is not architecturally visible, except as enabling thistransposed access mode.

The stream definition template provides the full structure of a streamthat contains data. The iteration counts and dimensions provide most ofthe structure, while the various flags provide the rest of the details.For all data-containing streams, the streaming engine defines a singlestream template. All stream types it supports fit this template. Thestreaming engine defines a six-level loop nest for addressing elementswithin the stream. Most of the fields in the stream template mapdirectly to the parameters in that algorithm. FIG. 29 illustrates streamtemplate register 2900. The numbers above the fields are bit numberswithin a 512-bit vector. Table 7 shows the stream field definitions of astream template.

TABLE 7 FIG. 29 Field Reference Size Name Number Description Bits ICNT02901 Iteration count for loop 0 32 ICNT1 2902 Iteration count for loop 132 ICNT2 2903 Iteration count for loop 2 32 ICNT3 2904 Iteration countfor loop 3 32 ICNT4 2905 Iteration count for loop 4 32 INCT5 2906Iteration count for loop 5 32 DIM1 2911 Signed dimension for loop 1 32DIM2 2912 Signed dimension for loop 2 32 DIM3 2913 Signed dimension forloop 3 32 DIM4 2914 Signed dimension for loop 4 32 DIM5 2915 Signeddimension for loop 5 32 FLAGS 2921 Stream modifier flags 64

Loop 0 is the innermost loop and loop 5 is the outermost loop. In thecurrent example DIM0 is always equal to is ELEM_BYTES definingphysically contiguous data. Thus the stream template register 2900 doesnot define DIM0. Streaming engine 2800 interprets all iteration countsas unsigned integers and all dimensions as unscaled signed integers. Aniteration count at any level (ICNT0, ICNT1, ICNT2, ICNT3, ICNT4 orICNT5) indicates an empty stream. Each iteration count must be at least1 to define a valid stream. The template above fully specifies the typeof elements, length and dimensions of the stream. The streaminstructions separately specify a start address. This would typically beby specification of a scalar register in scalar register file 211 whichstores this start address. This allows a program to open multiplestreams using the same template but different registers storing thestart address.

FIG. 30 illustrates sub-field definitions of the flags field 2921. Asshown in FIG. 30 the flags field 2921 is 8 bytes or 64 bits. FIG. 30shows bit numbers of the fields. Table 8 shows the definition of thesefields.

TABLE 8 FIG. 30 Reference Size Field Name Number Description Bits ELTYPE3001 Type of data element 4 TRANSPOSE 3002 Two dimensional transposemode 3 PROMOTE 3003 Promotion mode 3 VECLEN 3004 Stream vector length 3ELDUP 3005 Element duplication 3 GRDUP 3006 Group duplication 1 DECIM3007 Element decimation 2 THROTTLE 3008 Fetch ahead throttle mode 2DIMFMT 3009 Stream dimensions format 3 DIR 3010 Stream direction 1 0forward direction 1 reverse direction CBK0 3011 First circular blocksize number 4 CBK1 3012 Second circular block size number 4 AM0 3013Addressing mode for loop 0 2 AM1 3014 Addressing mode for loop 1 2 AM23015 Addressing mode for loop 2 2 AM3 3016 Addressing mode for loop 3 2AM4 3017 Addressing mode for loop 4 2 AM5 3018 Addressing mode for loop5 2

The Element Type (ELTYPE) field 3001 defines the data type of theelements in the stream. The coding of the four bits of the ELTYPE field3001 is defined as shown in Table 9.

TABLE 9 Sub-element Total Element ELTYPE Real/Complex Size Bits SizeBits 0000 real 8 8 0001 real 16 16 0010 real 32 32 0011 real 64 64 0100reserved 0101 reserved 0110 reserved 0111 reserved 1000 complex 8 16 noswap 1001 complex 16 32 no swap 1010 complex 32 64 no swap 1011 complex64 128 no swap 1100 complex 8 16 swapped 1101 complex 16 32 swapped 1110complex 32 64 swapped 1111 complex 64 128 swapped

Real/Complex Type determines whether the streaming engine treats eachelement as a real number or two parts (real/imaginary ormagnitude/angle) of a complex number. This field also specifies whetherto swap the two parts of complex numbers. Complex types have a totalelement size that is twice their sub-element size. Otherwise, thesub-element size equals total element size.

Sub-Element Size determines the type for purposes of type promotion andvector lane width. For example, 16-bit sub-elements get promoted to32-bit sub-elements or 64-bit sub-elements when a stream requests typepromotion. The vector lane width matters when central processing unitcore 110 operates in big endian mode, as it always lays out vectors inlittle endian order.

Total Element Size determines the minimal granularity of the stream. Inthe stream addressing model, it determines the number of bytes thestream fetches for each iteration of the innermost loop. Streams alwaysread whole elements, either in increasing or decreasing order.Therefore, the innermost dimension of a stream spansICNT0×total-element-size bytes.

The TRANSPOSE field 3002 determines whether the streaming engineaccesses the stream in a transposed order. The transposed orderexchanges the inner two addressing levels. The TRANSPOSE field 3002 alsoindicated the granularity it transposes the stream. The coding of thethree bits of the TRANSPOSE field 3002 is defined as shown in Table 10for normal 2D operations.

TABLE 10 Transpose Meaning 000 Transpose disabled 001 Transpose on 8-bitboundaries 010 Transpose on 16-bit boundaries 011 Transpose on 32-bitboundaries 100 Transpose on 64-bit boundaries 101 Transpose on 128-bitboundaries 110 Transpose on 256-bit boundaries 111 Reserved

Streaming engine 2800 may transpose data elements at a differentgranularity than the element size. This allows programs to fetchmultiple columns of elements from each row. The transpose granularitymust be no smaller than the element size. The TRANSPOSE field 3002interacts with the DIMFMT field 3009 in a manner further describedbelow.

The PROMOTE field 3003 controls whether the streaming engine promotessub-elements in the stream and the type of promotion. When enabled,streaming engine 2800 promotes types by powers-of-2 sizes. The coding ofthe three bits of the PROMOTE field 3003 is defined as shown in Table11.

TABLE 11 Promotion Promotion Resulting Sub-element Size PROMOTE FactorType 8-bit 16-bit 32-bit 64-bit 000 1x N/A  8-bit 16-bit 32-bit 64-bit001 2x zero extend 16-bit 32-bit 64-bit Invalid 010 4x zero extend32-bit 64-bit Invalid Invalid 011 8x zero extend 64-bit Invalid InvalidInvalid 100 reserved 101 2x sign extend 16-bit 32-bit 64-bit Invalid 1104x sign extend 32-bit 64-bit Invalid Invalid 111 8x sign extend 64-bitInvalid Invalid Invalid

When PROMOTE is 000, corresponding to a 1× promotion, each sub-elementis unchanged and occupies a vector lane equal in width to the sizespecified by ELTYPE. When PROMOTE is 001, corresponding to a 2×promotion and zero extend, each sub-element is treated as an unsignedinteger and zero extended to a vector lane twice the width specified byELTYPE. A 2× promotion is invalid for an initial sub-element size of 64bits. When PROMOTE is 010, corresponding to a 4× promotion and zeroextend, each sub-element is treated as an unsigned integer and zeroextended to a vector lane four times the width specified by ELTYPE. A 4×promotion is invalid for an initial sub-element size of 32 or 64 bits.When PROMOTE is 011, corresponding to an 8× promotion and zero extend,each sub-element is treated as an unsigned integer and zero extended toa vector lane eight times the width specified by ELTYPE. An 8× promotionis invalid for an initial sub-element size of 16, 32 or 64 bits. WhenPROMOTE is 101, corresponding to a 2× promotion and sign extend, eachsub-element is treated as a signed integer and sign extended to a vectorlane twice the width specified by ELTYPE. A 2× promotion is invalid foran initial sub-element size of 64 bits. When PROMOTE is 110,corresponding to a 4× promotion and sign extend, each sub-element istreated as a signed integer and sign extended to a vector lane fourtimes the width specified by ELTYPE. A 4× promotion is invalid for aninitial sub-element size of 32 or 64 bits. When PROMOTE is 111,corresponding to an 8× promotion and zero extend, each sub-element istreated as a signed integer and sign extended to a vector lane eighttimes the width specified by ELTYPE. An 8× promotion is invalid for aninitial sub-element size of 16, 32 or 64 bits.

The VECLEN field 3004 defines the stream vector length for the stream inbytes. Streaming engine 2800 breaks the stream into groups of elementsthat are VECLEN bytes long. The coding of the three bits of the VECLENfield 3004 is defined as shown in Table 12.

TABLE 12 VECLEN Stream Vector Length 000  1 byte 001  2 bytes 010  4bytes 011  8 bytes 100 16 bytes 101 32 bytes 110 64 bytes 111 Reserved

VECLEN must be greater than or equal to the product of the element sizein bytes and the duplication factor. As shown in Table 11, the maximumVECLEN of 64 bytes equals the preferred vector size of vector datapathside B 116. When VECLEN is shorter than the native vector width ofcentral processing unit core 110, streaming engine 2800 pads the extralanes in the vector provided to central processing unit core 110. TheGRDUP field 3006 determines the type of padding. The VECLEN field 3004interacts with ELDUP field 3005 and GRDUP field 3006 in a mannerdetailed below.

The ELDUP field 3005 specifies a number of times to duplicate eachelement. The element size multiplied with the element duplication amountmust not exceed the 64 bytes. The coding of the three bits of the ELDUPfield 3005 is defined as shown in Table 13.

TABLE 13 ELDUP Duplication Factor 000 No Duplication 001  2 times 010  4times 011  8 times 100 16 times 101 32 times 110 64 times 111 Reserved

The ELDUP field 3005 interacts with VECLEN field 3004 and GRDUP field3006 in a manner detailed below. The nature of the relationship betweenthe permitted element size, element duplication factor and destinationvector length requires that a duplicated element that overflows thefirst destination register will fill an integer number of destinationregisters upon completion of duplication. The data of these additionaldestination registers eventually supplies the corresponding stream headregister 2818/2828. Upon completion of duplication of a first dataelement, the next data element is rotated down to the least significantbits discarding the first data element. The process then repeats forthis new data element.

The GRDUP bit 3006 determines whether group duplication is enabled. IfGRDUP bit 3006 is 0, then group duplication is disabled. If the GRDUPbit 3006 is 1, then group duplication is enabled. When enabled by GRDUPbit 3006, streaming engine 2800 duplicates a group of elements to fillthe vector width. VECLEN field 3004 defines the length of the group toreplicate. When VECLEN field 3004 is less than the vector length ofcentral processing unit core 110 and GRDUP bit 3006 enables groupduplication, streaming engine 2800 fills the extra lanes (see FIGS. 21and 22 ) with additional copies of the stream vector. Because streamvector length and vector length of central processing unit core 110 arealways integral powers of two, group duplication always produces anintegral number of duplicate copies. Note GRDUP and VECLEN do notspecify the number of duplications. The number of duplications performedis based upon the ratio of VECLEN to the native vector length, which is64 bytes/512 bits in the preferred embodiment.

The GRDUP field 3006 specifies how stream engine 2800 pads streamvectors for bits following the VECLEN length out to the vector length ofcentral processing unit core 110. When GRDUP bit 3006 is 0, streamingengine 2800 fills the extra lanes with zeros and marks these extravector lanes invalid. When GRDUP bit 3006 is 1, streaming engine 2800fills extra lanes with copies of the group of elements in each streamvector. Setting GRDUP bit 3006 to 1 has no effect when VECLEN is set tothe native vector width of central processing unit core 110. VECLEN mustbe at least as large as the product of ELEM_BYTES and the elementduplication factor ELDUP. That is, an element or the duplication factornumber of elements cannot be separated using VECLEN.

Group duplication operates only to the destination vector size. Groupduplication does not change the data supplied when the product of theelement size ELEM_BYTES and element duplication factor ELDUP equals orexceeds the destination vector width. Under these conditions the stateof the GRDUP bit 3006 and the VECLEN field 3004 have no effect on thesupplied data.

Element duplication (ELDUP) and group duplication (GRUDP) areindependent. Note these features include independent specification andparameter setting. Thus element duplication and group duplication may beused together or separately. Because of how these are specified, elementduplication permits overflow to the next vector while group duplicationdoes not.

The DECIM field 3007 controls data element decimation of thecorresponding stream. Streaming engine 2800 deletes data elements fromthe stream upon storage in stream head registers 2818/2828 forpresentation to the requesting functional unit. Decimation alwaysremoves whole data elements, not sub-elements. The DECIM field 3007 isdefined as listed in Table 14.

TABLE 14 DECIM Decimation Factor 00 No Decimation 01 2 times 10 4 times11 Reserved

If DECIM field 3007 equals 00, then no decimation occurs. The dataelements are passed to the corresponding stream head registers 2818/2828without change. If DECIM field 3007 equals 01, then 2:1 decimationoccurs. Streaming engine 2800 removes odd number elements from the datastream upon storage in the stream head registers 2818/2828. Limitationsin the formatting network require 2:1 decimation to be employed withdata promotion by at least 2× (PROMOTE cannot be 000), ICNT0 must bemultiple of 2 and the total vector length (VECLEN) must be large enoughto hold a single promoted, duplicated element. For transposed streams(TRANSPOSE #0), the transpose granule must be at least twice the elementsize in bytes before promotion. If DECIM field 3007 equals 10, then 4:1decimation occurs. Streaming engine 2800 retains every fourth dataelement removing three elements from the data stream upon storage in thestream head registers 2818/2828. Limitations in the formatting networkrequire 4:1 decimation to be employed with data promotion by at least 4×(PROMOTE cannot be 000, 001 or 101), ICNT0 must be multiple of 4 and thetotal vector length (VECLEN) must be large enough to hold a singlepromoted, duplicated element. For transposed streams (TRANSPOSE #0),decimation always removes columns, and never removes rows. Thus thetranspose granule must be: at least twice the element size in bytesbefore promotion for 2:1 decimation (GRANULE 2×ELEM_BYTES); and at leastfour times the element size in bytes before promotion for 4:1 decimation(GRANULE 4×ELEM_BYTES).

The THROTTLE field 3008 controls how aggressively the streaming enginefetches ahead of central processing unit core 110. The coding of the twobits of this field is defined as shown in Table 15.

TABLE 15 THROTTLE Description 00 Minimum throttling, maximum fetch ahead01 Less throttling, more fetch ahead 10 More throttling, less fetchahead 11 Maximum throttling, minimum fetch ahead

THROTTLE does not change the meaning of the stream, and serves only as ahint. The streaming engine may ignore this field. Programs should notrely on the specific throttle behavior for program correctness, becausethe architecture does not specify the precise throttle behavior.THROTTLE allows programmers to provide hints to the hardware about theprogram's own behavior. By default, the streaming engine attempts to getas far ahead of central processing unit core 110 as it can to hide asmuch latency as possible (equivalent THOTTLE=11), while providing fullstream throughput to central processing unit core 110. While several keyapplications need this level of throughput, it can lead to bad systemlevel behavior for others. For example, the streaming engine discardsall fetched data across context switches. Therefore, aggressivefetch-ahead can lead to wasted bandwidth in a system with large numbersof context switches. Aggressive fetch-ahead only makes sense in thosesystems if central processing unit core 110 consumes data very quickly.

The DIMFMT field 3009 defines which of the loop count fields ICNT0 2901,ICNT1 2902, ICNT2 2903, ICNT3 2804, ICNT4 2905 and ICNT5 2906, of theloop dimension fields DIM1 2911, DIM2 2912, DIM3 2913, DIM4 2914 andDIM5 2915 and of the addressing mode fields AM0 3013, AM1 3014, AM23015, AM3 3016, AM4 3017 and AM5 3018 (part of FLAGS field 2921) of thestream template register 2900 that are active for that particularstream. Table 16 lists the active loops for various values of the DIMFMTfield 3009.

TABLE 16 DIMFMT Loop5 Loop4 Loop3 Loop2 Loop1 Loop0 000 InactiveInactive Inactive Inactive Inactive Active 001 Inactive InactiveInactive Inactive Active Active 010 Inactive Inactive Inactive ActiveActive Active 011 Inactive Inactive Active Active Active Active 100Inactive Active Active Active Active Active 101 Active Active ActiveActive Active Active 110-111 Reserved

Each active loop count must be at least 1. The outer active loop countmust be greater than 1. (An outer active loop count of 1 is no differentthan corresponding a stream with one fewer loop.)

The DIR bit 3010 determines the direction of fetch of the inner loop(Loop0). If the DIR bit 3010 is 0 then Loop0 fetches are in the forwarddirection toward increasing addresses. If the DIR bit 3010 is 1 thenLoop0 fetches are in the backward direction toward decreasing addresses.The fetch direction of other loops is determined by the sign of thecorresponding loop dimension DIM1, DIM2, DIM3, DIM4 and DIM5 which aresigned integers.

The CBK0 field 3011 and the CBK1 field 3012 control the circular blocksize upon selection of circular addressing. The manner of determiningthe circular block size will be more fully described below.

The AM0 field 3013, AM1 field 3014, AM2 field 3015, AM3 field 3016, AM4field 3017 and AM5 field 3018 control the addressing mode of acorresponding loop. This permits the addressing mode to be independentlyspecified for each loop. Each of AM0 field 3013, AM1 field 3014, AM2field 3015, AM3 field 3016, AM4 field 3017 and AM5 field 3018 are threebits and are decoded as listed in Table 17.

TABLE 17 AMx field Meaning 00 Linear addressing 01 Circular addressingblock size set by CBK0 10 Circular addressing block size set by CBK0 +CBK1 + 1 11 reserved

In linear addressing the address advances according to the addressarithmetic whether forward or reverse. In circular addressing theaddress remains within a defined address block. Upon reaching the end ofthe circular address block the address wraps around to other limit ofthe block. Circular addressing blocks are typically limited to 2^(N)addresses where N is an integer. Circular address arithmetic may operateby cutting the carry chain between bits and not allowing a selectednumber of most significant bits to change. Thus arithmetic beyond theend of the circular block changes only the least significant bits.

The block size is set as listed in Table 18.

TABLE 18 Encoded Block Size CBK0 or CBK0 + CBK1 + 1 Block Size (bytes) 0512 1  1 K 2  2 K 3  4 K 4  8 K 5  16 K 6  32 K 7  64 K 8 128 K 9 256 K10 512 K 11  1 M 12  2 M 13  4 M 14  8 M 15  16 M 16  32 M 17  64 M 18128 M 19 256 M 20 512 M 21  1 G 22  2 G 23  4 G 24  8 G 25 16 G 26 32 G27 64 G 28 Reserved 29 Reserved 30 Reserved 31 Reserved

In the preferred embodiment the circular block size is set by the numberencoded by CBK0 (first circular address mode 01) or the number encodedby CBK0+CBK1+1 (second circular address mode 10). For example the firstcircular address mode, the circular address block size can be from 512bytes to 16 M bytes. For the second circular address mode, the circularaddress block size can be from 1 K bytes to 64 G bytes. Thus the encodedblock size is 2^((B+9)) bytes, where B is the encoded block number whichis CBK0 for the first block size (AMx of 01) and CBK0+CBK1+1 for thesecond block size (AMx of 10).

The central processing unit 110 exposes the streaming engine to programsthrough a small number of instructions and specialized registers. ASTROPEN instruction opens a stream. The STROPEN command specifies astream number indicating opening stream 0 or stream 1. The STROPENcommand specifies a data register storing the start address of thestream. The STROPEN specifies a stream template register which storesthe stream template as described above. The arguments of the STROPENinstruction are listed in Table 19.

TABLE 19 Argument Description Stream Start Address Scalar registerstoring stream start address Register Steam Number Stream 0 or Stream 1Stream Template Vector register storing stream template data Register

The stream start address register is preferably a register in generalscalar register file 211. The STROPEN instruction may specify thisstream start address register via scr1 field 1305. The STROPENinstruction specifies stream 0 or stream 1 by its opcode. The streamtemplate register is preferably a vector register in general vectorregister file 231. The STROPEN instruction may specify this streamtemplate register via scr2/cst field 1304. If the specified stream isactive the STROPEN instruction closes the prior stream and replaces thestream with the specified stream.

A STRSAVE instruction captures sufficient state information of aspecified stream to restart that stream in the future. A STRRSTRinstruction restores a previously saved stream. A STRSAVE instructiondoes not save any of the data of the stream. A STRSAVE instruction savesonly metadata. The stream re-fetches stream data in response to aSTRRSTR instruction.

As noted above there are circumstances when some data within a streamholding register 2818 or 2828 are not valid. As described above thiscould occur at the end of an inner loop when the number of streamelements is less than the stream holding register 2818/2828 size. Thiscould also occur at the end of an inner loop when the number of streamelements remaining is less than the lanes defined by VECLEN. For timesnot at the end of an inner loop, if VECLEN is less than the width ofstream holding register 2818/2828 and GRDUP is disabled, then lanes instream holding register 2818/2828 in excess of VECLEN are invalid.

Normally, streaming engine 2800 loops through all elements in all nestedloops defined by a stream's parameters. There are instances that aprogram may need to skip some elements in the stream. In some instances,often dependent upon a data determination, it is advisable to exit astream early or to exit one of the nested loops early. Processor 100provides a set of instructions triggering early loop exit. Theseinstructions are in the form SEBRKn, where n is the loop level. Theseloop break instructions break from one or more levels of loop nestbetween vectors of elements. Stream breaks always happen at vectorboundaries. A stream break skips the remaining elements in loop levelnamed and all inner loops. The stream resumes at the next iteration ofthe next outer loop. If the named loop level is the outer level(generally SEBRK5), then the stream ends.

FIG. 31 illustrates a partial schematic view of address generator 2811.Address generator 2811 forms an address for fetching a next element inthe defined stream of the corresponding streaming engine based on astart address register 3101 and loop address values for each of thevarious loops (e.g., Loop0, Loop1, Loop2, Loop3, Loop4, Loop5, etc.)using a final sum adder 3103. Start address register 3101 stores a startaddress of the data stream. As previously described, start addressregister 3101 is preferably a scalar register in global scalar registerfile 211 designated by the STROPEN instruction that opened thecorresponding stream. As known in the art, this start address may becopied from the specified scalar register and stored locally at thecorresponding address generator 2811/2821. A first loop of the streamemploys Loop0 count register 3111, adder 3112, multiplier 3113 andcomparator 3114. Loop0 count register 3111 stores the working copy ofthe iteration count of the first loop (Loop0). For each iteration ofLoop0 adder 3112, as triggered by the Next Address signal, adds 1 to theloop count, which is stored back in Loop0 count register 3111.Multiplier 3113 multiplies the current loop count and the quantityELEM_BYTES. ELEM_BYTES is the size of each data element in loop0 inbytes. Loop0 traverses data elements physically contiguous in memorywith an iteration step size of ELEM_BYTES.

Comparator 3114 compares the count stored in Loop0 count register 3111(after incrementing by adder 3112) with the value of ICNT0 2901 from thecorresponding stream template register 2900. When the output of adder3112 equals the value of ICNT0 2910 of the stream template register2900, an iteration of Loop0 is complete. Comparator 3114 generates anactive Loop0 End signal. Loop0 count register 3111 is reset to 0 and aniteration of the next higher loop, in this case Loop1, is triggered.

FIG. 31 also illustrates the mechanism for early exit from loop0.Receipt of a SEBRK0 instruction is interpreted by instruction decodeunit 113 as a command to set the single bit in the BREAK0 flag 3115. Theoutput of BREAK0 flag 3115 supplies one input of AND gate 3116. A vectorboundary signal supplied other input of AND gate 3116. This vectorboundary signal is active when the corresponding head register 2818/2828is filled. There are several cases when head register 2818/2828 isconsidered full. Head register 2818/2828 is considered full when thefinal lane is populated with a data element. This would typically be inthe middle of an iteration of loop0 when the remaining data elements isloop0 exceeds the number of lanes. Head register 2818/2828 is alsoconsidered full when a last data element in loop0 is loaded. As notedabove, when the number of available lanes exceeds the number of dataelements in loop0, then excess lanes are filled with 0's and markedinvalid. Vector boundary is active upon this event. As described above,if the parameter VECLEN is less than the length of head register2818/2828 these same two cases occur upon filling lanes up to VECLENamount. Generally the number of remaining data elements will exceed theremaining lanes as controlled by VECLEN. In that case, vector boundaryis active when the lanes as reduced by VECLEN are filled. If the numberof remaining data elements is less than the number of lanes as reducedby VECLEN, vector boundary is active when the last remaining dataelement is stored in head register 2818/2828. vector boundary is setinactive upon beginning storing new set of data elements in headregister 2818/2828.

AND gate 3116 generates an active Loop0 End signal the same ascomparator 3114, when the BREAK0 flag 3115 and vector boundary are bothactive. This resets Loop0 count register 3111 to 0 and triggers aniteration of Loop1, the next higher loop. Thus a loop break instructionSEBRK0 ends a current iteration of Loop0 and triggers the next iterationof Loop1 on the next vector boundary.

Circuits for the higher loops (Loop1, Loop2, Loop3, Loop4 and Loop5) aresimilar to that illustrated in FIG. 31 . Each loop includes acorresponding working loop count register, adder, multiplier,comparator, break register and AND gate. The adder of each loop istriggered by the loop end signal of the prior loop. The second input toeach multiplier is the corresponding dimension DIM1, DIM2, DIM3, DIM4and DIM5 from the corresponding stream template. The comparator of eachloop compares the working loop register count with the correspondingiteration value ICNT1, ICNT2, ICNT3, ICNT4 and ICNT5 of thecorresponding stream template register 2900. A loop end signal generatesan iteration of the next higher loop. A loop end signal from loop5 endsthe stream. A SEBRKn instruction ends that current iteration of Loopnthe same as completing the loop, except on the next vector boundary,that is the next full head register 2818/2828. A SEBRKn instructiontriggers an iteration of the n+1 loop. If n is the outer loop, then thestream ends.

Stream break instructions may operate differently depending on thenumber of loops enabled by DIMFMT. A stream break instruction specifyinga loop level greater than the number of loops enabled by DIMFMT ends thestream. Attempts to read data elements past this end returns all 0's foreach data element and all lanes are marked invalid. Table 20 lists theactive loops ended for various stream break instructions and values ofthe DIMFMT field 3009.

TABLE 20 DIMFMT SEBRK5 SEBRK4 SEBRK3 SEBRK2 SEBRK1 SEBRK0 000 Ends EndsEnds Ends Ends Ends Stream Stream Stream Stream Stream Stream 001 EndsEnds Ends Ends Ends Ends Stream Stream Stream Stream Stream Loop0 010Ends Ends Ends Ends Ends Ends Stream Stream Stream Stream Loop1 Loop0011 Ends Ends Ends Ends Ends Ends Stream Stream Stream Loop2 Loop1 Loop0100 Ends Ends Ends Ends Ends Ends Stream Stream Loop3 Loop2 Loop1 Loop0101 Ends Ends Ends Ends Ends Ends Stream Loop4 Loop3 Loop2 Loop1 Loop0110-111 ReservedIf DIMFMT selects a single loop, then any stream break instruction endsthe stream. A SEBRK5 instruction ends the stream for any value ofDIMFMT.

Stream break instructions may operate differently based upon theTRANSPOSE mode. If TRANSPOSE is active (TRANSPOSE field 3002≠000) thenthe meanings of Loop0 and Loop1 are exchanged. Table 21 lists the activeloops ended for various stream break instructions and values of theDIMFMT field 3009 when TRANSPOSE is active.

TABLE 21 DIMFMT SEBRK5 SEBRK4 SEBRK3 SEBRK2 SEBRK1 SEBRK0 000 Ends EndsEnds Ends Ends Ends Stream Stream Stream Stream Stream Stream 001 EndsEnds Ends Ends Ends Ends Stream Stream Stream Stream Loop0 Stream 010Ends Ends Ends Ends Ends Ends Stream Stream Stream Stream Loop0 Loop1011 Ends Ends Ends Ends Ends Ends Stream Stream Stream Loop2 Loop0 Loop1100 Ends Ends Ends Ends Ends Ends Stream Stream Loop3 Loop2 Loop0 Loop1101 Ends Ends Ends Ends Ends Ends Stream Loop4 Loop3 Loop2 Loop0 Loop1110-111 Reserved

FIG. 32 is a partial schematic diagram 3200 illustrating the streaminput operand coding described above. FIG. 32 illustrates decoding srclfield 1305 of one instruction of a corresponding src1 input offunctional unit 3220. These same circuits may be duplicated for src2/cstfield 1304 of an instruction controlling functional unit 3220. Inaddition, these circuits are duplicated for each instruction capable ofemploying stream data as an operand within an execute packet that can bedispatched simultaneously.

Instruction decoder 113 receives bits 13 to 17 comprising srcl field1305 of an instruction. The opcode field (bits 3 to 12 for allinstructions and additionally bits 28 to 31 for unconditionalinstructions) unambiguously specifies a corresponding functional unit3220 and the function to be performed. In this embodiment functionalunit 3220 could be L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244 orC unit 245. The relevant part of instruction decoder 113 illustrated inFIG. 32 decodes src1 bit field 1305. Sub-decoder 3211 determines whethersrcl bit field 1305 is in the range from 00000 to 01111. If this is thecase, sub-decoder 3211 supplies a corresponding register number toglobal vector register file 231. In this example this register number isthe four least significant bits of src1 bit field 1305. Global vectorregister file 231 recalls data stored in the register corresponding tothis register number and supplies this data to the src1 input offunctional unit 3220. This decoding is generally known in the art.

Sub-decoder 3212 determines whether srcl bit field 1305 is in the rangefrom 10000 to 10111. If this is the case, sub-decoder 3212 supplies acorresponding register number to the corresponding local vector registerfile. If the instruction is directed to L2 unit 241 or S2 unit 242, thecorresponding local vector register file is local vector register file232. If the instruction is directed to M2 unit 243, N2 unit 244 or Cunit 245, the corresponding local vector register file is local vectorregister file 233. In this example this register number is the threeleast significant bits of src1 bit field 1305. The corresponding localvector register file 232/233 recalls data stored in the registercorresponding to this register number and supplies this data to the src1input of functional unit 3220. This decoding is generally known in theart.

Sub-decoder 3213 determines whether srcl bit field 1305 is 11100. Ifthis is the case, sub-decoder 3213 supplies a stream 0 read signal tostreaming engine 2800. Streaming engine 2800 then supplies stream 0 datastored in holding register 2818 to the src1 input of functional unit3220.

Sub-decoder 3214 determines whether srcl bit field 1305 is 11101. Ifthis is the case, sub-decoder 3214 supplies a stream 0 read signal tostreaming engine 2800. Streaming engine 2800 then supplies stream 0 datastored in holding register 2818 to the src1 input of functional unit3220. Sub-decoder 3214 also supplies an advance signal to stream 0. Aspreviously described, streaming engine 2800 advances to store the nextsequential vector of data elements of stream 0 in holding register 2818.

Sub-decoder 3215 determines whether src1 bit field 1305 is 11110. Ifthis is the case, sub-decoder 3215 supplies a stream 1 read signal tostreaming engine 2800. Streaming engine 2800 then supplies stream 1 datastored in holding register 2828 to the src1 input of functional unit3220.

Sub-decoder 3216 determines whether src1 bit field 1305 is 11111. Ifthis is the case, sub-decoder 3216 supplies a stream 1 read signal tostreaming engine 2800. Streaming engine 2800 then supplies stream 1 datastored in holding register 2828 to the src1 input of functional unit3220. Sub-decoder 3214 also supplies an advance signal to stream 1. Aspreviously described, streaming engine 2800 advances to store the nextsequential vector of data elements of stream 1 in holding register 2828.

The exact number of instruction bits devoted to operand specificationand the number of data registers and streams are design choices. Thoseskilled in the art would realize that other number selections thandescribed in the application are feasible. In particular, thespecification of a single global vector register file and omission oflocal vector register files is feasible. This invention employs a bitcoding of an input operand selection field to designate a stream readand another bit coding to designate a stream read and advancing thestream.

This process illustrated in FIG. 32 automatically transfers valid datainto predicate register file 234 each time stream data is read. Thisvalid data may then be used by P unit 246 for further calculation ofmeta data. This valid data may also be used as a mask or as an operandfor other operations by one or more of vector datapath side B 116functional units including L2 unit 241, S2 unit 242, M2 unit 243, N2unit 244 and C unit 245. There are numerous feasible compound logicoperations employing this stream valid data.

What is claimed is:
 1. A device comprising: a processor core thatincludes an instruction decoder; a memory control circuit coupled to theprocessor core that includes an address generator circuit and a registercoupled to the address generator circuit; and a cache memory coupled tothe memory control circuit and configure to store a set of data; whereinthe instruction decoder is configured to: based on a first instruction:initiate generation, using the memory control circuit, of a set ofaddresses associated with the set of data; and initiate retrieval of theset of data from the cache memory using the set of addresses; and basedon a second instruction, cause a value to be stored in the register; andwherein the memory control circuit is configured to interrupt thegeneration of the set of addresses based on the value stored in theregister.
 2. The device of claim 1, wherein: the generation of the setof addresses uses a set of nested loops; the second instructionspecifies a first loop of the set of nested loops; and the memorycontrol circuit is configured to interrupt the generation of the set ofaddresses by prematurely ending a current iteration of the first loopand beginning a next iteration of a second loop in which the first loopis nested.
 3. The device of claim 2, wherein: the processor coreincludes a stream template register; and the stream template register isconfigured to store a stream template that specifies total numbers ofiterations for the set of nested loops.
 4. The device of claim 3,wherein the stream template further specifies a number of loops in theset of nested loops.
 5. The device of claim 1, wherein: the generationof the set of addresses uses a set of nested loops that includes anoutermost loop; and the memory control circuit is configured tointerrupt the generation of the set of addresses by prematurely endinggeneration of the set of addresses based on the second instructionspecifying the outermost loop.
 6. The device of claim 1, wherein: theregister is a first register; the memory control circuit includes asecond register that is configured to assert a status signal; and thememory control circuit is configured to interrupt the generation of theset of addresses based on the value stored in the register and on thestatus signal being asserted.
 7. The device of claim 6, wherein thesecond register is configured to assert the status signal based on thesecond register being full.
 8. The device of claim 6, wherein: thegeneration of the set of addresses uses a set of nested loops thatincludes an innermost loop; and the second register is configured toassert the status signal based on a last data element of the set of datathat is associated with the innermost loop being stored in the secondregister.
 9. A device comprising: a memory control circuit that includesa register and that is configured to couple to a cache memory; aprocessor core coupled to the memory control circuit and configured to:receive a first instruction that specifies to open a data stream; basedon the first instruction: cause the memory control circuit to startgeneration of a set of addresses associated with the data stream; andcause the memory control circuit to start retrieval of the data streamusing the set of addresses; receive a second instruction; and based onthe second instruction, cause a value to be stored in the register thatis configured to interrupt the generation of the set of addresses. 10.The device of claim 9, wherein: the generation of the set of addressesuses a set of nested loops; the second instruction specifies a firstloop of the set of nested loops; and the memory control circuit isconfigured to interrupt the generation of the set of addresses byprematurely ending a current iteration of the first loop and beginning anext iteration of a second loop in which the first loop is nested. 11.The device of claim 10, wherein: the processor core includes a streamtemplate register; and the stream template register is configured tostore a stream template that specifies total numbers of iterations forthe set of nested loops.
 12. The device of claim 11, wherein the streamtemplate further specifies a number of loops in the set of nested loops.13. The device of claim 9, wherein: the generation of the set ofaddresses uses a set of nested loops that includes an outermost loop;and the memory control circuit is configured to interrupt the generationof the set of addresses by prematurely ending generation of the set ofaddresses based on the second instruction specifying the outermost loop.14. The device of claim 9, wherein: the register is a first register;the memory control circuit includes a second register that is configuredto assert a status signal; and the memory control circuit is configuredto interrupt the generation of the set of addresses based on the valuestored in the register and on the status signal being asserted.
 15. Thedevice of claim 14, wherein the second register is configured to assertthe status signal based on the second register being full.
 16. Thedevice of claim 14, wherein: the generation of the set of addresses usesa set of nested loops that includes an innermost loop; and the secondregister is configured to assert the status signal based on a last dataelement of the set of data that is associated with the innermost loopbeing stored in the second register.
 17. A method comprising: receivinga first instruction to retrieve a set of data from a memory; and basedon the first instruction: beginning generation of a set of addressesassociated with the set of data; and beginning retrieval of the set ofdata from the memory; and receiving a second instruction; based on thesecond instruction, causing a value to be stored in a register; based onthe value, interrupting the generation of the set of addresses.
 18. Themethod of claim 17, wherein: the generation of the set of addresses usesa set of nested loops; and the interrupting of the generation of the setof addresses includes prematurely ending a current iteration of a firstloop and beginning a next iteration of a second loop in which the firstloop is nested.
 19. The method of claim 17, wherein: the generation ofthe set of addresses uses a set of nested loops that includes anoutermost loop; and the interrupting of the generation of the set ofaddresses includes prematurely ending generation of the set of addressesbased on the second instruction specifying the outermost loop.
 20. Themethod of claim 17, wherein: the register is a first register; themethod further comprises asserting a status signal based on a status ofa second register; and the interrupting of the generation of the set ofaddresses is further based on the status signal being asserted.